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authorOlof Johansson <olof@lixom.net>2014-05-30 21:18:55 -0700
committerOlof Johansson <olof@lixom.net>2014-05-30 21:18:55 -0700
commit8792f59213c3fc39a7f407f27975cce38fbb1b6d (patch)
treec917195b6454066728f3ad66fa3b535f008d1159 /include
parentb4c48e8780325e1f2ba79ccc0fb2a6c99c7cfac2 (diff)
parente7ef0b632eb45b0c725629da3561ecde8935a398 (diff)
Merge tag 'samsung-clk-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Merge "Samsung 3rd clock updates for 3.16" from Kukjin Kim: - add clock for new exynos5410 SoC * tag 'samsung-clk-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: clk: exynos5410: register clocks using common clock framework Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/exynos5410.h33
1 files changed, 33 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
new file mode 100644
index 000000000000..9b180f032e2d
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -0,0 +1,33 @@
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+
+/* core clocks */
+#define CLK_FIN_PLL 1
+#define CLK_FOUT_APLL 2
+#define CLK_FOUT_CPLL 3
+#define CLK_FOUT_MPLL 4
+#define CLK_FOUT_BPLL 5
+#define CLK_FOUT_KPLL 6
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0 128
+#define CLK_SCLK_UART1 129
+#define CLK_SCLK_UART2 130
+#define CLK_SCLK_UART3 131
+#define CLK_SCLK_MMC0 132
+#define CLK_SCLK_MMC1 133
+#define CLK_SCLK_MMC2 134
+
+/* gate clocks */
+#define CLK_UART0 257
+#define CLK_UART1 258
+#define CLK_UART2 259
+#define CLK_UART3 260
+#define CLK_MCT 315
+#define CLK_MMC0 351
+#define CLK_MMC1 352
+#define CLK_MMC2 353
+
+#define CLK_NR_CLKS 512
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */