Serial: tegra: Allow 2% error in selecting clock source for baudrate.

Allowing 2% error in calculated baudrate when finding the best clock
source uart controller.

bug 870388

Change-Id: Id765efd7bf087e10bc93a8ba5bd1eec8a8f3ef48
Reviewed-on: http://git-master/r/50255
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

1 files changed, 12 insertions, 0 deletions

diff --git a/include/linux/tegra_uart.h b/include/linux/tegra_uart.h
index 3d35e217cbca..42d981982b64 100644
--- a/include/linux/tegra_uart.h
+++ b/include/linux/tegra_uart.h
@@ -28,6 +28,18 @@ struct uart_clk_parent {
 	unsigned long	fixed_clk_rate;
 };
 
+/*
+ * struct tegra_uart_platform_data - Platform data for tegra high speed uart.
+ *
+ * @parent_clk_list: The parent clock source list. The best clock source will be
+ *                   selected such that the error between desired baudrate and
+ *                   calculated baudrate within 2% error. The searching will
+ *                   start from index 0 and so the preference of clock source
+ *                   selection will be high on index 0 and it will go lower
+ *                   with increasing index.
+ * @parent_clk_count: The number of clock source list.
+ */
+
 struct tegra_uart_platform_data {
 	void (*wake_peer)(struct uart_port *);
 	struct uart_clk_parent *parent_clk_list;