ENGR00334447 [imx6qdl] Fix random failures caused by ddr frequency change procedure

Backport busfreq patch from 3.10.x kernel:
2d1f2b76919e13d8744cc8579316c002f832c675

The ddr frequency change code was responsible for some random kernel crashes.
This was due to the fact that L1 and L2 caches were not correctly flushed/synced
during the frequency change procedure.
This patch attempts to fix the issue by:
1. Ensure that every active core put into wfe flushes and disables its L1.
2. All cores (except the one executing the ddr freq change code) informs the SCU
that it going into a power down state after flushing and disabling its L1. It
also removes itself out the SMP cluster.
3. Variables shared across cores are stored in non-cacheable IRAM space.
4. SCU power status register is used to identify if all cores have reached a quiscent state
before the core running the ddr freq change code proceeds further.

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>

0 files changed, 0 insertions, 0 deletions