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| author | Yixun Lan <yixun.lan@amlogic.com> | 2017-11-07 22:12:23 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-03-22 09:17:54 +0100 |
| commit | 05fafb80ba2412da75ef8e23f37bec2285ac7f6f (patch) | |
| tree | a4ec4854d67a102227c473bb7e657189f6a86f5d /kernel/sched | |
| parent | e95928a6407f32c716f11a4483e6438f88a0ed9f (diff) | |
clk: meson: gxbb: fix wrong clock for SARADC/SANA
[ Upstream commit 75eccf5ed83250c0aeaeeb76f7288254ac0a87b4 ]
According to the datasheet, in Meson-GXBB/GXL series,
The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
Test passed at gxl-s905x-p212 board.
The following published datasheets are wrong and should be updated
[1] GXBB v1.1.4
[2] GXL v0.3_20170314
Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
Tested-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'kernel/sched')
0 files changed, 0 insertions, 0 deletions