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| author | Bin Meng <bmeng.cn@gmail.com> | 2017-09-11 02:41:54 -0700 |
|---|---|---|
| committer | Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> | 2017-10-11 09:43:13 +0200 |
| commit | db2ce7f3c7b01a6a3611fb8e0bfa453dec168a47 (patch) | |
| tree | df5ef4a1c38c78ed37576ff6813cd19e9ccfd137 /kernel/up.c | |
| parent | 9d63f17661e25fd28714dac94bdebc4ff5b75f09 (diff) | |
spi-nor: intel-spi: Check transfer length in the HW/SW cycle
Intel SPI controller only has a 64 bytes FIFO. This adds a sanity
check before triggering any HW/SW sequencer work.
Additionally for the SW sequencer, if given data length is zero,
we should not mark the 'Data Cycle' bit.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Diffstat (limited to 'kernel/up.c')
0 files changed, 0 insertions, 0 deletions