diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-08-23 22:57:50 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-08-23 23:32:56 -0500 |
| commit | 804a4d36965cec49025174cf25f3f784aba41e32 (patch) | |
| tree | 8453998d9ed876e23f0eb94990a734fe3643f52f /lib/syscall.c | |
| parent | aece51a192d8a1bb1eb7302519d5ab9699f18551 (diff) | |
ENGR00221277 MX6DL/S - Set AXI clock to 270MHz
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from periph_clk just before the DDR
freq is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'lib/syscall.c')
0 files changed, 0 insertions, 0 deletions