diff options
| author | Alex Frid <afrid@nvidia.com> | 2010-03-31 20:06:27 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-04-01 16:49:30 -0800 |
| commit | ccbaa3ec2afb825c315d11e34b30faffa10c199e (patch) | |
| tree | 7d5af2580e998a119baf149adfdb24cbde633659 /net/lapb/lapb_timer.c | |
| parent | 0f29062f22c119d305eec613bfae1b2c8a6983f4 (diff) | |
tegra RM: Updated VDE clock configuration policy.
Updated VDE clock configuration policy - allowed to use high frequency
PLLC for VDE targets within 100MHz-200MHz range. This range was covered
by low frequency PLLP0, but better divider granularity achieved with PLLC
results in lower voltage requirements.
Change-Id: I922dbd8db19dc19339db5bfbf2651604e28e789d
Reviewed-on: http://git-master/r/1007
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Sharad Ranjan <shranjan@nvidia.com>
Tested-by: Sharad Ranjan <shranjan@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'net/lapb/lapb_timer.c')
0 files changed, 0 insertions, 0 deletions