diff options
| author | Rabin Vincent <rabin@rab.in> | 2016-01-05 18:34:04 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-01-06 01:32:09 -0500 |
| commit | f941461c925832fbeb7876b794ab9fbec6a7a8af (patch) | |
| tree | 96cca8032172841f4514e2f5e721c09b38f368b4 /net/sched/sch_generic.c | |
| parent | 60aa3b080a3d2b408af2ca114edb3efc84ad1838 (diff) | |
ARM: net: bpf: fix zero right shift
The LSR instruction cannot be used to perform a zero right shift since a
0 as the immediate value (imm5) in the LSR instruction encoding means
that a shift of 32 is perfomed. See DecodeIMMShift() in the ARM ARM.
Make the JIT skip generation of the LSR if a zero-shift is requested.
This was found using american fuzzy lop.
Signed-off-by: Rabin Vincent <rabin@rab.in>
Acked-by: Alexei Starovoitov <ast@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/sched/sch_generic.c')
0 files changed, 0 insertions, 0 deletions