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| author | Stefan Agner <stefan@agner.ch> | 2016-02-08 12:50:13 -0800 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2016-06-27 08:58:31 +0200 |
| commit | 69ae5ad2e6e9840d769c487ecf25f4ce9d002b20 (patch) | |
| tree | 80d3f9380f62c1a80d770bf2e4a404367c31f752 /net/sunrpc/auth_gss/svcauth_gss.c | |
| parent | 7dedde1847c99c9ece645db5ebdf5237c8aa09d1 (diff) | |
drm/fsl-dcu: use bus_flags for pixel clock polarity
The drivers current default configuration drives the pixel data
on rising edge of the pixel clock. However, most display sample
data on rising edge... This leads to color shift artefacts visible
especially at edges.
This patch changes the relevant defines to be useful and actually
set the bits, and changes pixel clock polarity to drive the pixel
data on falling edge by default. The patch also adds an explicit
pixel clock polarity flag to the display introduced with the driver
(NEC WQVGA "nec,nl4827hc19-05b") using the new bus_flags field to
retain the initial behavior.
Signed-off-by: Stefan Agner <stefan@agner.ch>
(cherry picked from commit 2c80661d2ea9bac9bc7ba519097745829add1871)
[removed conflicting DISPLAY_FLAGS solution]
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'net/sunrpc/auth_gss/svcauth_gss.c')
0 files changed, 0 insertions, 0 deletions