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authorJon Mayo <jmayo@nvidia.com>2012-12-06 17:19:51 -0800
committerDan Willemsen <dwillemsen@nvidia.com>2013-09-14 12:46:11 -0700
commitd9d1fb88d19220ca2bcae2092f7e29da2a7f74fd (patch)
treecd4e1fb867a15cb9d62757a0546c699170c215b0 /sound/pci
parent016b3b5e71c6905a262705f8aade5dab4441b594 (diff)
ALSA: hda: powergate HDA when clock gating
Use powergating APIs to ensure that HDA and display play nice. Export powergate APIs so snd-intel-hda can be built as a module. Bug 1178366 Change-Id: I30559b9288fcbd86615a674756e70f04c9fb5d83 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/169245 Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'sound/pci')
-rw-r--r--sound/pci/hda/hda_intel.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index a45efd3b18f1..e65988de3330 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -67,6 +67,9 @@
#ifdef CONFIG_SND_HDA_VPR
#include <linux/nvmap.h>
#endif
+#ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
+#include <mach/powergate.h>
+#endif
static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
@@ -1512,10 +1515,17 @@ static void azx_platform_enable_clocks(struct azx *chip)
{
int i;
+#ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+ tegra_unpowergate_partition(TEGRA_POWERGATE_DISB);
+#endif
+#endif
+
for (i = 0; i < chip->platform_clk_count; i++)
clk_enable(chip->platform_clks[i]);
chip->platform_clk_enable++;
+
}
static void azx_platform_disable_clocks(struct azx *chip)
@@ -1528,6 +1538,12 @@ static void azx_platform_disable_clocks(struct azx *chip)
for (i = 0; i < chip->platform_clk_count; i++)
clk_disable(chip->platform_clks[i]);
+#ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+ tegra_powergate_partition(TEGRA_POWERGATE_DISB);
+#endif
+#endif
+
chip->platform_clk_enable--;
}
#endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */