diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2015-07-31 17:48:53 +0800 |
|---|---|---|
| committer | Octavian Purdila <octavian.purdila@nxp.com> | 2017-02-23 14:21:42 +0200 |
| commit | c76096c1ebb88306829f9c645f8cf11f8a3777c8 (patch) | |
| tree | cd1443bfce79d2b0fe1507934328a163a535bfba /sound/soc/codecs | |
| parent | e63b048ff8d946aeebd0a549645f27a007a69bd1 (diff) | |
MLK-11301: ASoC: cs42xx8: can't set volume 255 in idle mode
Volume 255 corresponding to register value 0, the value 0 is default
value. In regcache_sync(), when the cache value is equal to default
value, this register will be skipped. So volume 255 isn't set to
register successfully.
The correct fix is to add software reset in runtime_resume, but cs42xx8
has no software reset, the hardware reset gpio pin is used by all the
perpherial device in ARD base board. So need to use another method.
In order to fix it, need to cherry-pick two patch from master branch.
Which will sync all the registers include the register which cache value
equal the default value, And remove regcache_mark_dirty().
Add update value of one register to make the cache_dirty if user press
the hardware reset pin on the board, then need to regcache_sync.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 5c0cae19928f99ebc8adf0013df850ba5b41d6a8)
Diffstat (limited to 'sound/soc/codecs')
| -rw-r--r-- | sound/soc/codecs/cs42xx8.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/sound/soc/codecs/cs42xx8.c b/sound/soc/codecs/cs42xx8.c index 30ef63f1b85a..599f802f78bc 100644 --- a/sound/soc/codecs/cs42xx8.c +++ b/sound/soc/codecs/cs42xx8.c @@ -383,7 +383,6 @@ static struct snd_soc_dai_driver cs42xx8_dai = { }; static const struct reg_default cs42xx8_reg[] = { - { 0x01, 0x01 }, /* Chip I.D. and Revision Register */ { 0x02, 0x00 }, /* Power Control */ { 0x03, 0xF0 }, /* Functional Mode */ { 0x04, 0x46 }, /* Interface Formats */ @@ -628,9 +627,14 @@ static int cs42xx8_runtime_resume(struct device *dev) goto err_clk; } + regmap_update_bits(cs42xx8->regmap, CS42XX8_PWRCTL, + CS42XX8_PWRCTL_PDN_MASK, 1); /* Make sure hardware reset done */ msleep(5); + regmap_update_bits(cs42xx8->regmap, CS42XX8_PWRCTL, + CS42XX8_PWRCTL_PDN_MASK, 0); + regcache_cache_only(cs42xx8->regmap, false); ret = regcache_sync(cs42xx8->regmap); @@ -654,7 +658,6 @@ static int cs42xx8_runtime_suspend(struct device *dev) { struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev); - regcache_mark_dirty(cs42xx8->regmap); regcache_cache_only(cs42xx8->regmap, true); regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), |