diff options
| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2008-12-19 13:05:24 -0700 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2008-12-20 13:05:38 +0000 |
| commit | 07d8d9dca4615821d928f4b5087fdc61e292e1dc (patch) | |
| tree | 6be2915b8307bc1cb15e5fac7af8eaef9bd96769 /sound/soc/davinci/davinci-i2s.c | |
| parent | 69ab820c862250d460dfaaf82164972a4a69418a (diff) | |
ALSA: ASoC: DaVinci: document I2S limitations
DaVinci does not support true I2S or right justified
mode so not all I2S codecs will work with it when the codec is
master. Document this limitation.
Add dsp_a, dsp_b mode options
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/davinci/davinci-i2s.c')
| -rw-r--r-- | sound/soc/davinci/davinci-i2s.c | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index 24fe9db2c75e..51ceded8a245 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c @@ -241,10 +241,27 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1); xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1); switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_RIGHT_J: + case SND_SOC_DAIFMT_DSP_B: break; case SND_SOC_DAIFMT_I2S: - case SND_SOC_DAIFMT_DSP_B: + /* Davinci doesn't support TRUE I2S, but some codecs will have + * the left and right channels contiguous. This allows + * dsp_a mode to be used with an inverted normal frame clk. + * If your codec is master and does not have contiguous + * channels, then you will have sound on only one channel. + * Try using a different mode, or codec as slave. + * + * The TLV320AIC33 is an example of a codec where this works. + * It has a variable bit clock frequency allowing it to have + * valid data on every bit clock. + * + * The TLV320AIC23 is an example of a codec where this does not + * work. It has a fixed bit clock frequency with progressively + * more empty bit clock slots between channels as the sample + * rate is lowered. + */ + fmt ^= SND_SOC_DAIFMT_NB_IF; + case SND_SOC_DAIFMT_DSP_A: rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1); xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1); break; |