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authorShengjiu Wang <shengjiu.wang@nxp.com>2020-08-25 13:46:02 +0800
committerShengjiu Wang <shengjiu.wang@nxp.com>2020-08-31 18:08:17 +0800
commit3184f6eabe276bea8d3b7e5448bbce634efd3941 (patch)
treea474249e95467f4e21521c9178a8a51be6768915 /sound/soc/fsl/fsl_esai.h
parentd5986dc1d41899a11bd636fe337ef7d503183683 (diff)
MLK-24612-2: ASoC: fsl_esai: Add esai mix driver
ESAI mixer is for mixing the data from clients. There is a ping-pong buffer in the mixer for storing the mixed data. The period size is same as the period size in client (unit is sample number). Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Zhang <peng.zhang_8@nxp.com>
Diffstat (limited to 'sound/soc/fsl/fsl_esai.h')
-rw-r--r--sound/soc/fsl/fsl_esai.h70
1 files changed, 70 insertions, 0 deletions
diff --git a/sound/soc/fsl/fsl_esai.h b/sound/soc/fsl/fsl_esai.h
index f873588d9045..628d711ac214 100644
--- a/sound/soc/fsl/fsl_esai.h
+++ b/sound/soc/fsl/fsl_esai.h
@@ -10,6 +10,9 @@
#ifndef _FSL_ESAI_DAI_H
#define _FSL_ESAI_DAI_H
+#include <sound/dmaengine_pcm.h>
+#include "fsl_esai_mix.h"
+
/* ESAI Register Map */
#define REG_ESAI_ETDR 0x00
#define REG_ESAI_ERDR 0x04
@@ -348,4 +351,71 @@
#define ESAI_RX_DIV_PSR 3
#define ESAI_RX_DIV_PM 4
#define ESAI_RX_DIV_FP 5
+
+/**
+ * fsl_esai_soc_data: soc specific data
+ *
+ * @imx: for imx platform
+ * @reset_at_xrun: flags for enable reset operaton
+ * @use_edma: edma is used.
+ */
+struct fsl_esai_soc_data {
+ bool imx;
+ bool reset_at_xrun;
+ bool use_edma;
+};
+
+/**
+ * fsl_esai: ESAI private data
+ *
+ * @dma_params_rx: DMA parameters for receive channel
+ * @dma_params_tx: DMA parameters for transmit channel
+ * @pdev: platform device pointer
+ * @regmap: regmap handler
+ * @coreclk: clock source to access register
+ * @extalclk: esai clock source to derive HCK, SCK and FS
+ * @fsysclk: system clock source to derive HCK, SCK and FS
+ * @spbaclk: SPBA clock (optional, depending on SoC design)
+ * @soc: soc specific data
+ * @lock: spin lock between hw_reset() and trigger()
+ * @fifo_depth: depth of tx/rx FIFO
+ * @slot_width: width of each DAI slot
+ * @slots: number of slots
+ * @channels: channel num for tx or rx
+ * @hck_rate: clock rate of desired HCKx clock
+ * @sck_rate: clock rate of desired SCKx clock
+ * @hck_dir: the direction of HCKx pads
+ * @sck_div: if using PSR/PM dividers for SCKx clock
+ * @slave_mode: if fully using DAI slave mode
+ * @synchronous: if using tx/rx synchronous mode
+ * @sw_mix: enable sw mix in driver
+ * @name: driver name
+ */
+struct fsl_esai {
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ struct clk *coreclk;
+ struct clk *extalclk;
+ struct clk *fsysclk;
+ struct clk *spbaclk;
+ const struct fsl_esai_soc_data *soc;
+ struct fsl_esai_mix mix[2];
+ spinlock_t lock; /* Protect hw_reset and trigger */
+ u32 fifo_depth;
+ u32 slot_width;
+ u32 slots;
+ u32 tx_mask;
+ u32 rx_mask;
+ u32 channels[2];
+ u32 hck_rate[2];
+ u32 sck_rate[2];
+ bool hck_dir[2];
+ bool sck_div[2];
+ bool slave_mode[2];
+ bool synchronous;
+ bool sw_mix;
+ char name[32];
+};
#endif /* _FSL_ESAI_DAI_H */