ASoC: fsl_micfil: fix PDM root clock frequency

Depending on sample rate the PDM must be clocked at either 24.576MHz or
22.5792MHz. CLK_DIV is later calculated as function of PDM root clock
frequency and FS. Setting PDM root clock = FS * 1024 is wrong because
for low sample rate such as 8000 the PDM root clock will be 8000 * 1024
= 8192000 Hz so PDM will be underclocked for this sample rate.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>

1 files changed, 6 insertions, 3 deletions

diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 22826d48244b..59efd823906f 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -1353,6 +1353,9 @@ static inline bool clk_in_list(struct clk *p, struct clk *clk_src[])
 	return false;
 }
 
+#define CLK_8K_FREQ    24576000
+#define CLK_11K_FREQ   22579200
+
 static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil, int clk_id,
 				    unsigned int freq)
 {
@@ -1426,10 +1429,10 @@ static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil, int clk_id,
 				 "failed to set parrent %d\n", ret);
 	}
 
-	ret = clk_set_rate(micfil->mclk, freq * 1024);
+	clk_rate = freq % 8000 == 0 ? CLK_8K_FREQ : CLK_11K_FREQ;
+	ret = clk_set_rate(micfil->mclk, clk_rate);
 	if (ret)
-		dev_warn(dev, "failed to set rate (%u): %d\n",
-			 freq * 1024, ret);
+		dev_warn(dev, "failed to set rate (%llu): %d\n", clk_rate, ret);
 	clk_prepare_enable(micfil->mclk);
 
 	return ret;