diff options
| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2019-09-03 10:38:00 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:52:43 +0800 |
| commit | 7ac5c8b94ae6dbcd1867acb8d27b03507d55ebf2 (patch) | |
| tree | c6f91b39af6c4e8000cff566bc184f80dedf5a54 /sound/soc/fsl/fsl_micfil.h | |
| parent | 219d54332a09e8d8741c1e1982f5eae56099de85 (diff) | |
ASoC: fsl_micfil: Merge the changes from imx_4.19.y
Merge the changes from imx_4.19.y
The top commit is:
b5472e3f3dd1 ("MLK-21775-4: ASoC: fsl_micfil: synchronize HWVAD enable/disable")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'sound/soc/fsl/fsl_micfil.h')
| -rw-r--r-- | sound/soc/fsl/fsl_micfil.h | 53 |
1 files changed, 50 insertions, 3 deletions
diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h index bac825c3135a..14ad08b6b150 100644 --- a/sound/soc/fsl/fsl_micfil.h +++ b/sound/soc/fsl/fsl_micfil.h @@ -258,6 +258,40 @@ #define MICFIL_VAD0_STAT_IF_MASK BIT(MICFIL_VAD0_STAT_IF_SHIFT) #define MICFIL_VAD0_STAT_IF BIT(MICFIL_VAD0_STAT_IF_SHIFT) +/* HWVAD Constants */ +#define MICFIL_HWVAD_ENVELOPE_MODE 0 +#define MICFIL_HWVAD_ENERGY_MODE 1 +#define MICFIL_HWVAD_INIT_FRAMES 10 +#define MICFIL_HWVAD_INPGAIN 0 +#define MICFIL_HWVAD_SGAIN 6 +#define MICFIL_HWVAD_NGAIN 3 +#define MICFIL_HWVAD_NFILADJ 0 +#define MICFIL_HWVAD_ZCDADJ (1 << (MICFIL_VAD0_ZCD_ZCDADJ_WIDTH - 2)) +#define MICFIL_HWVAD_ZCDTH 10 /* initial threshold value */ +#define MICFIL_HWVAD_ZCDOR 0 +#define MICFIL_HWVAD_ZCDAND 1 +#define MICFIL_HWVAD_ZCD_MANUAL 0 +#define MICFIL_HWVAD_ZCD_AUTO 1 +#define MICFIL_HWVAD_HPF_BYPASS 0 +#define MICFIL_HWVAD_HPF_1750HZ 1 +#define MICFIL_HWVAD_HPF_215HZ 2 +#define MICFIL_HWVAD_HPF_102HZ 3 +#define MICFIL_HWVAD_FRAMET_DEFAULT 10 + +/* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */ +#define MICFIL_DC_CTRL_SHIFT 0 +#define MICFIL_DC_CTRL_MASK 0xFFFF +#define MICFIL_DC_CTRL_WIDTH 2 +#define MICFIL_DC_CHX_SHIFT(v) (2 * (v)) +#define MICFIL_DC_CHX_MASK(v) ((BIT(MICFIL_DC_CTRL_WIDTH) - 1) \ + << MICFIL_DC_CHX_SHIFT(v)) +#define MICFIL_DC_MODE(v1, v2) (((v1) << MICFIL_DC_CHX_SHIFT(v2)) \ + & MICFIL_DC_CHX_MASK(v2)) +#define MICFIL_DC_CUTOFF_21HZ 0 +#define MICFIL_DC_CUTOFF_83HZ 1 +#define MICFIL_DC_CUTOFF_152Hz 2 +#define MICFIL_DC_BYPASS 3 + /* MICFIL Output Control Register */ #define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v)) @@ -273,11 +307,24 @@ #define FIFO_PTRWID 3 #define FIFO_LEN BIT(FIFO_PTRWID) -#define MICFIL_IRQ_LINES 2 +#define MICFIL_IRQ_LINES 4 #define MICFIL_MAX_RETRY 25 -#define MICFIL_SLEEP_MIN 90000 /* in us */ -#define MICFIL_SLEEP_MAX 100000 /* in us */ +#define MICFIL_SLEEP 100 /* in ms */ #define MICFIL_DMA_MAXBURST_RX 6 #define MICFIL_CTRL2_OSR_DEFAULT (0 << MICFIL_CTRL2_CICOSR_SHIFT) +#define MICFIL_DEFAULT_RATE 48000 +#define MICFIL_CLK_SRC_NUM 3 +#define MICFIL_CLK_AUTO 0 + +/* clock source ids */ +#define MICFIL_AUDIO_PLL1 0 +#define MICFIL_AUDIO_PLL2 1 +#define MICFIL_CLK_EXT3 2 + +/* States of micfil */ +#define MICFIL_HWVAD_OFF 0 +#define MICFIL_HWVAD_ON 1 +#define MICFIL_RECORDING_OFF 0 +#define MICFIL_RECORDING_ON 1 #endif /* _FSL_MICFIL_H */ |