diff options
| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2018-01-23 13:26:37 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:53:50 +0800 |
| commit | 15e50be3635bb61fdefc65327efc3f378d3ffb60 (patch) | |
| tree | f21cf5b806868e513a437e484a73df95915add4d /sound/soc/fsl/fsl_sai.h | |
| parent | 82a7f067a1461350596569f61cfa313947228159 (diff) | |
MLK-16224-4: ASoC: fsl_sai: support multi fifo and DSD
The codec always mux the LRCLK pin to DSD data line, so when
we want to support DSD, the pinmux is different. For two channel
DSD, the DSDL is mapped to TX0, but the DSDR is mapped to TX4,
there is address offset for the fifo address of TX0 and TX4, TX4's
fifo is not adjacent to TX0's.
Usually, if mapping is TX0 and TX1, that will be easy for SAI
and SDMA to handle, that SAI can use the FIFO combine mode, SDMA
can use the normal script.
so for DSD:
1. The SDMA should use the multi-fifo script, and SAI can't
use the FIFO combine mode.
2. driver should to check the dts configuration(fsl,dataline) for
which dataline is used corrently
3. maxburst is the multiply of datalines
4. each channel of DSD occupy one data lane
5. according to data lane, set TRCE bits
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
Diffstat (limited to 'sound/soc/fsl/fsl_sai.h')
| -rw-r--r-- | sound/soc/fsl/fsl_sai.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 5ea60c0171a7..017967c5b305 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -11,7 +11,10 @@ #define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ SNDRV_PCM_FMTBIT_S24_LE |\ - SNDRV_PCM_FMTBIT_S32_LE) + SNDRV_PCM_FMTBIT_S32_LE |\ + SNDRV_PCM_FMTBIT_DSD_U8 |\ + SNDRV_PCM_FMTBIT_DSD_U16_LE |\ + SNDRV_PCM_FMTBIT_DSD_U32_LE) /* SAI Register Map Register */ #define FSL_SAI_TCSR(offset) (0x00 + offset) /* SAI Transmit Control */ @@ -172,9 +175,14 @@ struct fsl_sai { bool slave_mode[2]; bool is_lsb_first; bool is_dsp_mode; + bool is_multi_lane; bool synchronous[2]; bool is_stream_opened[2]; + bool is_dsd; unsigned int dataline[2]; + unsigned int dataline_dsd[2]; + unsigned int dataline_off[2]; + unsigned int dataline_off_dsd[2]; unsigned int masterflag[2]; unsigned int mclk_id[2]; @@ -187,6 +195,8 @@ struct fsl_sai { struct snd_dmaengine_dai_dma_data dma_params_tx; const struct fsl_sai_soc_data *soc; struct pm_qos_request pm_qos_req; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_dsd; }; #define TX 1 |