diff options
| author | Viorel Suman <viorel.suman@nxp.com> | 2020-05-14 11:16:51 +0300 |
|---|---|---|
| committer | Viorel Suman <viorel.suman@nxp.com> | 2020-05-15 10:15:43 +0300 |
| commit | ae30f694dad4fcbcba09e895505211f29d0a83ae (patch) | |
| tree | bfcc68940eb5413f57823a6e8b5a44253d67c788 /sound/soc/fsl/fsl_spdif.c | |
| parent | 16346350984e9f613f8ef5945b14c4ce7c0d6e65 (diff) | |
MLK-24043-2: ASoC: fsl_xcvr: do not rise M0+ SPDIF TX interrupt
At SPDIF TX interrupt the firmware running on M0+ core
overwrites TX DPATH BYPASS FEM bit which turns the
expected PHY DMAC TX PLL clock 2*bitclock instead of
expected 10*bitclock if SAI PLL is used as PHY DMAC TX
PLL.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'sound/soc/fsl/fsl_spdif.c')
0 files changed, 0 insertions, 0 deletions