diff options
author | Viorel Suman <viorel.suman@nxp.com> | 2019-04-18 15:25:44 +0300 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:54:23 +0800 |
commit | ccea8f42a786297d39a70dff869764faeede7404 (patch) | |
tree | 848df11e18150d8efb27b35193560c283246c782 /sound/soc/fsl/fsl_spdif.c | |
parent | 8e013fb268248049cc221513f6562b90882b4fc8 (diff) |
MLK-21484-2: ASoC: fsl_spdif: ensure clk is unprepared before reparent
On recent kernels clks which are marked with CLK_SET_RATE_GATE are
"protected" against further changes at clk_prepare time, including clk
reparent. Wrap clk set_parent and set_rate operations with
disable_unprepare and prepare_enable.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Diffstat (limited to 'sound/soc/fsl/fsl_spdif.c')
-rw-r--r-- | sound/soc/fsl/fsl_spdif.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index a91d785461fd..4de132a064b6 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c @@ -750,6 +750,7 @@ static int fsl_spdif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, struct clk *clk, *p, *pll = 0, *npll = 0; u64 ratio = freq; int ret, i; + bool reparent = false; if (dir != SND_SOC_CLOCK_OUT || freq == 0 || clk_id != STC_TXCLK_SPDIF_ROOT) return 0; @@ -775,23 +776,22 @@ static int fsl_spdif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, p = pp; } - if (pll) { - npll = (do_div(ratio, 8000) ? data->pll11k_clk : data->pll8k_clk); - if (!clk_is_match(pll, npll)) { - ret = clk_set_parent(p, npll); - if (ret < 0) - dev_warn(cpu_dai->dev, - "failed to set parent %s: %d\n", - __clk_get_name(npll), ret); - } + npll = (do_div(ratio, 8000) ? data->pll11k_clk : data->pll8k_clk); + reparent = (pll && !clk_is_match(pll, npll)); + + clk_disable_unprepare(clk); + if (reparent) { + ret = clk_set_parent(p, npll); + if (ret < 0) + dev_warn(cpu_dai->dev, "failed to set parent %s: %d\n", + __clk_get_name(npll), ret); } ret = clk_set_rate(clk, freq); - if (ret < 0) { - dev_err(cpu_dai->dev, "failed to set clock rate (%u): %d\n", - freq, ret); - return ret; - } + if (ret < 0) + dev_warn(cpu_dai->dev, "failed to set clock rate (%u): %d\n", + freq, ret); + clk_prepare_enable(clk); for (i = 0; i < SPDIF_TXRATE_MAX; i++) { ret = fsl_spdif_probe_txclk(data, i); |