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authorShengjiu Wang <shengjiu.wang@nxp.com>2020-03-17 18:27:37 +0800
committerShengjiu Wang <shengjiu.wang@nxp.com>2020-03-18 15:42:07 +0800
commitd55d453fdfe18971d93473be7d2de44eb602914b (patch)
treefe0fa881daf24dc4a82e818175bd5569beb488ae /sound/soc/fsl/fsl_spdif.c
parentd91068f32271da2b3c0dfc36143d2db07dff8f3e (diff)
MLK-23618-11: ASoC: fsl_spdif: Don't bind clock with regmap
The call flow: devm_regmap_init_mmio_clk - clk_prepare() - clk_pm_runtime_get() Cause the power domain of lpcg clock always be enabled. which impact the power consumption. So we can't bind clock with regmap, then explicitly enable clock when using. As we already enable all clock in pm_runtime_resume, so only need to enable clock in probe. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Diffstat (limited to 'sound/soc/fsl/fsl_spdif.c')
-rw-r--r--sound/soc/fsl/fsl_spdif.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index c691ae2b4284..2cccf527eeec 100644
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -1392,7 +1392,7 @@ static int fsl_spdif_probe(struct platform_device *pdev)
return PTR_ERR(regs);
spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
- "core", regs, &fsl_spdif_regmap_config);
+ NULL, regs, &fsl_spdif_regmap_config);
if (IS_ERR(spdif_priv->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(spdif_priv->regmap);
@@ -1494,10 +1494,16 @@ static int fsl_spdif_probe(struct platform_device *pdev)
spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
- /*Clear the val bit for Tx*/
+ ret = clk_prepare_enable(spdif_priv->coreclk);
+ if (ret)
+ return ret;
+
+ /*Cleer the val bit for Tx*/
regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SCR,
SCR_VAL_MASK, 1 << SCR_VAL_OFFSET);
+ clk_disable_unprepare(spdif_priv->coreclk);
+
pm_runtime_enable(&pdev->dev);
/* Register with ASoC */