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author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2020-03-17 18:27:16 +0800 |
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committer | Shengjiu Wang <shengjiu.wang@nxp.com> | 2020-03-18 15:42:03 +0800 |
commit | d91068f32271da2b3c0dfc36143d2db07dff8f3e (patch) | |
tree | 84feaeb343f975b74df727298ae7b31c6585a40d /sound/soc/fsl/fsl_spdif.c | |
parent | c2641e1974f7f1a0e858fd227eb233085d6da9bb (diff) |
MLK-23618-10: ASoC: fsl_esai: Don't bind clock with regmap
The call flow:
devm_regmap_init_mmio_clk
- clk_prepare()
- clk_pm_runtime_get()
Cause the power domain of lpcg clock always be enabled.
which impact the power consumption.
So we can't bind clock with regmap, then explicitly enable
clock when using. As we already enable all clock in
pm_runtime_resume, so only need to enable clock in probe.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Diffstat (limited to 'sound/soc/fsl/fsl_spdif.c')
0 files changed, 0 insertions, 0 deletions