diff options
| author | Viorel Suman <viorel.suman@nxp.com> | 2020-03-31 10:16:56 +0300 |
|---|---|---|
| committer | Viorel Suman <viorel.suman@nxp.com> | 2020-04-02 11:57:02 +0300 |
| commit | 2513444554dc5519512710da930530edbb993a6a (patch) | |
| tree | 798b748a97d50d4566c07c29fc64157861ac20b0 /sound/soc/fsl/fsl_xcvr.h | |
| parent | ca5fccb261bcd67f87562a622946d2c1f7448a12 (diff) | |
MLK-23732: fsl_xcvr: implement eARC RX fallback mode
There are 2 configurable options for eARC RX fallback
to ARC mode: "ARC single ended" or "ARC common".
Add amixer control in order to allow setting it
from userspace.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'sound/soc/fsl/fsl_xcvr.h')
| -rw-r--r-- | sound/soc/fsl/fsl_xcvr.h | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/sound/soc/fsl/fsl_xcvr.h b/sound/soc/fsl/fsl_xcvr.h index 424f6572747f..c51c88a6c69d 100644 --- a/sound/soc/fsl/fsl_xcvr.h +++ b/sound/soc/fsl/fsl_xcvr.h @@ -104,6 +104,21 @@ #define FSL_XCVR_EXT_CTRL_PAGE(i) (((i) << FSL_XCVR_EXT_CTRL_PAGE_SHFT) \ & FSL_XCVR_EXT_CTRL_PAGE_MASK) +#define FSL_XCVR_EXT_STUS_NT_FIFO_ENTR GENMASK(7, 0) +#define FSL_XCVR_EXT_STUS_NR_FIFO_ENTR GENMASK(15, 8) +#define FSL_XCVR_EXT_STUS_CM0_SLEEPING BIT(16) +#define FSL_XCVR_EXT_STUS_CM0_DEEP_SLP BIT(17) +#define FSL_XCVR_EXT_STUS_CM0_SLP_HACK BIT(18) +#define FSL_XCVR_EXT_STUS_RX_CMDC_RSTO BIT(23) +#define FSL_XCVR_EXT_STUS_TX_CMDC_RSTO BIT(24) +#define FSL_XCVR_EXT_STUS_RX_CMDC_COTO BIT(25) +#define FSL_XCVR_EXT_STUS_TX_CMDC_COTO BIT(26) +#define FSL_XCVR_EXT_STUS_HB_STATUS BIT(27) +#define FSL_XCVR_EXT_STUS_NEW_UD4_REC BIT(28) +#define FSL_XCVR_EXT_STUS_NEW_UD5_REC BIT(29) +#define FSL_XCVR_EXT_STUS_NEW_UD6_REC BIT(30) +#define FSL_XCVR_EXT_STUS_HPD_INPUT BIT(31) + #define FSL_XCVR_IRQ_NEW_CS BIT(0) #define FSL_XCVR_IRQ_NEW_UD BIT(1) #define FSL_XCVR_IRQ_MUTE BIT(2) @@ -132,12 +147,17 @@ FSL_XCVR_IRQ_MUTE | \ FSL_XCVR_IRQ_FIFO_UOFL_ERR | \ FSL_XCVR_IRQ_HOST_WAKEUP | \ + FSL_XCVR_IRQ_CMDC_STATUS_UPD | \ FSL_XCVR_IRQ_ARC_MODE #define FSL_XCVR_ISR_CMDC_TX_EN BIT(3) #define FSL_XCVR_ISR_HPD_TGL BIT(15) -#define FSL_XCVR_ISR_SET_SPDIF_MODE(t) (t ? BIT(21) : BIT(20)) #define FSL_XCVR_ISR_DMAC_SPARE_INT BIT(19) +#define FSL_XCVR_ISR_SET_SPDIF_RX_INT BIT(20) +#define FSL_XCVR_ISR_SET_SPDIF_TX_INT BIT(21) +#define FSL_XCVR_ISR_SET_SPDIF_MODE(t) (t ? BIT(21) : BIT(20)) +#define FSL_XCVR_ISR_SET_ARC_CM_INT BIT(22) +#define FSL_XCVR_ISR_SET_ARC_SE_INT BIT(23) #define FSL_XCVR_PHY_AI_ADDR_MASK GENMASK(7, 0) #define FSL_XCVR_PHY_AI_RESETN BIT(15) |