diff options
| author | Viorel Suman <viorel.suman@nxp.com> | 2020-03-30 18:32:53 +0300 |
|---|---|---|
| committer | Viorel Suman <viorel.suman@nxp.com> | 2020-04-01 16:07:34 +0300 |
| commit | 86401d592b3c0e8d30136628ade7690601ff17ba (patch) | |
| tree | 07a3c7c249107a0c5c6287ac82f269a54bbb63f4 /sound/soc/fsl/fsl_xcvr.h | |
| parent | c80c65a8601e22941db9ef3115e1578ba3296587 (diff) | |
MLK-23725-1: ASoC: fsl_xcvr: reimplement CS read function
CS_DATA registers are supposed to be used by M0+
core, according to block guide host core must read
channel status structure from data memory.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'sound/soc/fsl/fsl_xcvr.h')
| -rw-r--r-- | sound/soc/fsl/fsl_xcvr.h | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/sound/soc/fsl/fsl_xcvr.h b/sound/soc/fsl/fsl_xcvr.h index 1b982f5ee405..424f6572747f 100644 --- a/sound/soc/fsl/fsl_xcvr.h +++ b/sound/soc/fsl/fsl_xcvr.h @@ -58,12 +58,7 @@ #define FSL_XCVR_RX_DPTH_CTRL_SET 0x184 #define FSL_XCVR_RX_DPTH_CTRL_CLR 0x188 #define FSL_XCVR_RX_DPTH_CTRL_TOG 0x18c -#define FSL_XCVR_RX_CS_DATA_0 0x190 /* RX channel status bits regs */ -#define FSL_XCVR_RX_CS_DATA_1 0x194 -#define FSL_XCVR_RX_CS_DATA_2 0x198 -#define FSL_XCVR_RX_CS_DATA_3 0x19C -#define FSL_XCVR_RX_CS_DATA_4 0x1A0 -#define FSL_XCVR_RX_CS_DATA_5 0x1A4 + #define FSL_XCVR_TX_DPTH_CTRL 0x220 /* TX datapath ctrl reg */ #define FSL_XCVR_TX_DPTH_CTRL_SET 0x224 #define FSL_XCVR_TX_DPTH_CTRL_CLR 0x228 @@ -217,4 +212,10 @@ #define FSL_XCVR_CS_DATA_1_CH_16 0xB000 #define FSL_XCVR_CS_DATA_1_CH_32 0x3000 +/* Data memory structures */ +#define FSL_XCVR_RX_CS_CTRL_0 0x20 /* First RX CS control register */ +#define FSL_XCVR_RX_CS_CTRL_1 0x24 /* Second RX CS control register */ +#define FSL_XCVR_RX_CS_BUFF_0 0x80 /* First RX CS buffer */ +#define FSL_XCVR_RX_CS_BUFF_1 0xA0 /* Second RX CS buffer */ + #endif /* __FSL_XCVR_H */ |