diff options
| author | Viorel Suman <viorel.suman@nxp.com> | 2020-04-16 14:43:32 +0300 |
|---|---|---|
| committer | Viorel Suman <viorel.suman@nxp.com> | 2020-04-17 15:49:23 +0300 |
| commit | b164260078426fece986dc4020b8a69d9a2f6023 (patch) | |
| tree | 1e852e680bb444dddcf330821f02665f13a46b46 /sound/soc/fsl/fsl_xcvr.h | |
| parent | 7882f7f1391b2d6dcc9fca9a8248e3944b7ed008 (diff) | |
MLK-23567-2 ASoC: fsl_xcvr: enable SPDIF TX
Enable XCVR SPDIF TX mode.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'sound/soc/fsl/fsl_xcvr.h')
| -rw-r--r-- | sound/soc/fsl/fsl_xcvr.h | 30 |
1 files changed, 26 insertions, 4 deletions
diff --git a/sound/soc/fsl/fsl_xcvr.h b/sound/soc/fsl/fsl_xcvr.h index 4aa86ff954f8..ed7dd87c234a 100644 --- a/sound/soc/fsl/fsl_xcvr.h +++ b/sound/soc/fsl/fsl_xcvr.h @@ -8,10 +8,6 @@ #ifndef __FSL_XCVR_H #define __FSL_XCVR_H -#define FSL_XCVR_FORMATS (SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE) - -#define FSL_XCVR_AMODE_SPDIF (0x00 << 2) - #define FSL_XCVR_AMODE_SPDIF (0x00 << 2) #define FSL_XCVR_AMODE_ARC (0x01 << 2) #define FSL_XCVR_AMODE_EARC (0x02 << 2) @@ -211,6 +207,32 @@ #define FSL_XCVR_TX_DPTH_CTRL_CLK_RATIO BIT(29) #define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME GENMASK(31,30) +#define FSL_XCVR_PHY_AI_CTRL_AI_RESETN BIT(15) + +#define FSL_XCVR_PLL_CTRL0 0x00 +#define FSL_XCVR_PLL_CTRL0_SET 0x04 +#define FSL_XCVR_PLL_CTRL0_CLR 0x08 +#define FSL_XCVR_PLL_NUM 0x20 +#define FSL_XCVR_PLL_DEN 0x30 +#define FSL_XCVR_PLL_PDIV 0x40 +#define FSL_XCVR_PLL_BANDGAP_SET 0x54 +#define FSL_XCVR_PHY_CTRL 0x00 +#define FSL_XCVR_PHY_CTRL_SET 0x04 +#define FSL_XCVR_PHY_CTRL_CLR 0x08 +#define FSL_XCVR_PHY_CTRL2 0x70 +#define FSL_XCVR_PHY_CTRL2_SET 0x74 +#define FSL_XCVR_PHY_CTRL2_CLR 0x78 + +#define FSL_XCVR_PLL_BANDGAP_EN_VBG BIT(0) +#define FSL_XCVR_PLL_CTRL0_HROFF BIT(13) +#define FSL_XCVR_PLL_CTRL0_PWP BIT(14) +#define FSL_XCVR_PLL_CTRL0_CM0_EN BIT(24) + +#define FSL_XCVR_PHY_CTRL_PHY_EN BIT(0) +#define FSL_XCVR_PHY_CTRL_TSDIFF_OE BIT(5) +#define FSL_XCVR_PHY_CTRL_SPDIF_EN BIT(8) +#define FSL_XCVR_PHY_CTRL2_EARC_TXMS BIT(14) + #define FSL_XCVR_CS_DATA_0_FS_MASK GENMASK(31,24) #define FSL_XCVR_CS_DATA_0_FS_32000 0x3000000 #define FSL_XCVR_CS_DATA_0_FS_44100 0x0000000 |