diff options
| author | Viorel Suman <viorel.suman@nxp.com> | 2020-07-07 23:55:13 +0800 |
|---|---|---|
| committer | Viorel Suman <viorel.suman@nxp.com> | 2020-07-28 14:02:27 +0300 |
| commit | edfae0f3a63fa627dd07a5ecf640c00c186f3fbf (patch) | |
| tree | 8f769d7e0c7a5550b5bd4a34550a9f8c968edd37 /sound/soc/fsl/fsl_xcvr.h | |
| parent | 44d48993b96f76a61b29a1533db5b89144a00856 (diff) | |
MLK-24413: ASoC: fsl_xcvr: fix SPDIF RX/TX sequence issue
In SPDIF full duplex mode in order to get both RX and TX working we
need to start RX first, and TX second, fix this by porting SPDIF RX
configuration code from XCVR FW into Kernel driver and avoid using
M0+ core for SPDIF configuration.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'sound/soc/fsl/fsl_xcvr.h')
| -rw-r--r-- | sound/soc/fsl/fsl_xcvr.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sound/soc/fsl/fsl_xcvr.h b/sound/soc/fsl/fsl_xcvr.h index a2ae305e8e00..ca67e1b70221 100644 --- a/sound/soc/fsl/fsl_xcvr.h +++ b/sound/soc/fsl/fsl_xcvr.h @@ -220,10 +220,16 @@ #define FSL_XCVR_PLL_CTRL0_HROFF BIT(13) #define FSL_XCVR_PLL_CTRL0_PWP BIT(14) #define FSL_XCVR_PLL_CTRL0_CM0_EN BIT(24) +#define FSL_XCVR_PLL_CTRL0_CM1_EN BIT(25) +#define FSL_XCVR_PLL_CTRL0_CM2_EN BIT(26) +#define FSL_XCVR_PLL_PDIVx(v, i) ((v & 0x7) << (4 * i)) #define FSL_XCVR_PHY_CTRL_PHY_EN BIT(0) +#define FSL_XCVR_PHY_CTRL_RX_CM_EN BIT(1) #define FSL_XCVR_PHY_CTRL_TSDIFF_OE BIT(5) #define FSL_XCVR_PHY_CTRL_SPDIF_EN BIT(8) +#define FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN BIT(9) +#define FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN BIT(10) #define FSL_XCVR_PHY_CTRL_TX_CLK_MASK GENMASK(26, 25) #define FSL_XCVR_PHY_CTRL_TX_CLK_HDMI_SS BIT(25) #define FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS BIT(26) |