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authorSjoerd Simons <sjoerd.simons@collabora.co.uk>2015-11-25 09:54:11 +0100
committerMark Brown <broonie@kernel.org>2015-11-25 11:58:15 +0000
commit18a9d7486ad28d68920128720514f9555a4c1869 (patch)
treea6767d1da094048623a3faba8d4e2a4fb8982668 /sound/soc/rockchip
parent0e18d457b31e98e68f6918e41c85ad3b736c4789 (diff)
ASoC: rockchip: Fix incorrect VDW value for 24 bit
Correct valid data word register value for 24 bit data width. The bit value should be 10 (aka 0x2), not 0x10. This fixes playback of 24 bit audio. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/rockchip')
-rw-r--r--sound/soc/rockchip/rockchip_spdif.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/sound/soc/rockchip/rockchip_spdif.h b/sound/soc/rockchip/rockchip_spdif.h
index 07f86a21046a..921b4095fb92 100644
--- a/sound/soc/rockchip/rockchip_spdif.h
+++ b/sound/soc/rockchip/rockchip_spdif.h
@@ -28,9 +28,9 @@
#define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT)
#define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT)
-#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x00)
-#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x01)
-#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x10)
+#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0)
+#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1)
+#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2)
/*
* DMACR