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author | Alex Frid <afrid@nvidia.com> | 2011-01-22 23:16:44 -0800 |
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committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-01-25 15:27:08 -0800 |
commit | 92bf9f72fdf696de72de6186a1e1cd8818f3bb15 (patch) | |
tree | 95fa26bd0ace43c4fdcac5f2f1185c2cd6058b4f /sound/soc | |
parent | 4c583e3e70d08f78c7b0c0bb56d6b7115e7339fe (diff) |
ARM: tegra: dvfs: Update MPE dvfs table
Updated MPE clock dvfs table with recent characterization data.
As a result MPE clock limit is increased to 300MHz across all
tegra 2 SKUs.
Change-Id: Ibe700770c7d109a397cb140b6f217a8d48509ff1
Reviewed-on: http://git-master/r/16662
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Tested-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'sound/soc')
0 files changed, 0 insertions, 0 deletions