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authorViorel Suman <viorel.suman@nxp.com>2020-04-03 20:08:57 +0300
committerViorel Suman <viorel.suman@nxp.com>2020-04-16 15:45:10 +0300
commitded5d94919fbe559bda56756a02ae880cccbaf4b (patch)
tree80baf8f52b5a698e0284c8b0ab36de1343bb9293 /sound/soc
parentd4944201493570c1760a317367570fbde7c27808 (diff)
MLK-23799 fsl_xcvr: capabilities data structure support
Add an amixer interface which allows to load capabilities data structure. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'sound/soc')
-rw-r--r--sound/soc/fsl/fsl_xcvr.c52
-rw-r--r--sound/soc/fsl/fsl_xcvr.h1
2 files changed, 52 insertions, 1 deletions
diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index 6fbbf64c6f01..fce34bd13c51 100644
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -15,6 +15,8 @@
#include "fsl_xcvr.h"
#include "imx-pcm.h"
+#define FSL_XCVR_CAPDS_SIZE 256
+
struct fsl_xcvr {
struct platform_device *pdev;
struct regmap *regmap;
@@ -31,6 +33,7 @@ struct fsl_xcvr {
struct snd_dmaengine_dai_dma_data dma_prms_tx;
struct snd_aes_iec958 rx_iec958;
struct snd_aes_iec958 tx_iec958;
+ u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
};
static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, }; /* one bit 6, 12 ? */
@@ -507,13 +510,20 @@ err_firmware:
val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX);
/* disable DMA RD/WR */
mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
- val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
+ val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
+ /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
+ mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK;
+ val |= FSL_XCVR_EXT_CTRL_PAGE(8);
+
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
if (ret < 0) {
dev_err(dev, "Failed to set watermarks: %d\n", ret);
return ret;
}
+ /* Store Capabilities Data Structure into Data RAM */
+ memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds,
+ FSL_XCVR_CAPDS_SIZE);
return 0;
}
@@ -535,6 +545,15 @@ static int fsl_xcvr_type_bytes_info(struct snd_kcontrol *kcontrol,
return 0;
}
+static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
+ uinfo->count = FSL_XCVR_CAPDS_SIZE;
+
+ return 0;
+}
+
static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -568,6 +587,28 @@ static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol,
return 0;
}
+static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
+
+ memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE);
+
+ return 0;
+}
+
+static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
+
+ memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE);
+
+ return 0;
+}
+
static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -612,6 +653,15 @@ static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = {
},
SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum,
fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put),
+ /* Capabilities data structure, bytes */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "Capabilities Data Structure",
+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+ .info = fsl_xcvr_type_capds_bytes_info,
+ .get = fsl_xcvr_capds_get,
+ .put = fsl_xcvr_capds_put,
+ },
};
static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = {
diff --git a/sound/soc/fsl/fsl_xcvr.h b/sound/soc/fsl/fsl_xcvr.h
index c51c88a6c69d..4aa86ff954f8 100644
--- a/sound/soc/fsl/fsl_xcvr.h
+++ b/sound/soc/fsl/fsl_xcvr.h
@@ -237,5 +237,6 @@
#define FSL_XCVR_RX_CS_CTRL_1 0x24 /* Second RX CS control register */
#define FSL_XCVR_RX_CS_BUFF_0 0x80 /* First RX CS buffer */
#define FSL_XCVR_RX_CS_BUFF_1 0xA0 /* Second RX CS buffer */
+#define FSL_XCVR_CAP_DATA_STR 0x300 /* Capabilities data structure */
#endif /* __FSL_XCVR_H */