diff options
| author | Vinod G <vinodg@nvidia.com> | 2011-02-08 18:30:01 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-26 15:51:26 -0700 |
| commit | 3228d3dafcb8fb61ad7f7110a71b1086327209c6 (patch) | |
| tree | c7bf3f59938f923de406a3de071364ef1fc89c2b /sound | |
| parent | 35c71eb42abc893e567f6092a0474474087bc130 (diff) | |
arm: tegra: Enable digital mic for recording
Setting the Digital mic as default source for recording.
Original-Change-Id: I92037183731cc53fbc7e05b97ca4266c20740571
Reviewed-on: http://git-master/r/18827
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: Ic37b122948c376b3949965b42ee56429f5221385
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/tegra/tegra_soc_wm8903.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/sound/soc/tegra/tegra_soc_wm8903.c b/sound/soc/tegra/tegra_soc_wm8903.c index 59fc6ddd0c9a..27883f5e74ef 100644 --- a/sound/soc/tegra/tegra_soc_wm8903.c +++ b/sound/soc/tegra/tegra_soc_wm8903.c @@ -47,6 +47,10 @@ extern struct wired_jack_conf tegra_wired_jack_conf; #define B04_ADC_HPF_ENA 4 #define R20_SIDETONE_CTRL 32 #define R29_DRC_1 41 +#define B08_GP1_FN 8 +#define B07_GP1_DIR 7 +#define B08_GP2_FN 8 +#define B07_GP2_DIR 7 #define SET_REG_VAL(r,m,l,v) (((r)&(~((m)<<(l))))|(((v)&(m))<<(l))) @@ -149,6 +153,24 @@ static int tegra_hifi_hw_params(struct snd_pcm_substream *substream, CtrlReg = snd_soc_read(codec, R29_DRC_1); CtrlReg |= 0x3; /*mic volume 18 db */ snd_soc_write(codec, R29_DRC_1, CtrlReg); + + /* Enabling Digital mic as default*/ +#if !defined(CONFIG_ARCH_TEGRA_2x_SOC) + /* Set GP1_FN as DMIC_LR */ + CtrlReg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1); + CtrlReg = (0x06 << B08_GP1_FN) | (0x0 << B07_GP1_DIR); + snd_soc_write(codec, WM8903_GPIO_CONTROL_1, CtrlReg); + + /* Set GP2_FN as DMIC_DAT */ + CtrlReg = snd_soc_read(codec, WM8903_GPIO_CONTROL_2); + CtrlReg = (0x06 << B08_GP2_FN) | (0x1 << B07_GP2_DIR); + snd_soc_write(codec, WM8903_GPIO_CONTROL_2, CtrlReg); + + /* Enable DIG_MIC */ + CtrlReg = snd_soc_read(codec, WM8903_CLOCK_RATE_TEST_4); + CtrlReg = WM8903_ADC_DIG_MIC; + snd_soc_write(codec, WM8903_CLOCK_RATE_TEST_4, CtrlReg); +#endif } return 0; |