diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2016-10-24 10:15:37 +0800 |
|---|---|---|
| committer | Shengjiu Wang <shengjiu.wang@freescale.com> | 2017-02-10 10:14:27 +0800 |
| commit | 4f6b3da2333fd0341749f1a504a5faea88d5c839 (patch) | |
| tree | 5ff1373bfb7b53fcb41feab604a3ad4818a72426 /sound | |
| parent | 14fc7590563ed3d3247323133d89d606ae79b4fa (diff) | |
MLK-13418: ASoC: wm8960: workaround no sound issue in master mode
The input MCLK is 12.288MHz, The desired output sysclk is 11.2896MHz
the sample rate is 44100Hz, with the pllprescale=2, postscale=sysclkdiv=1,
some chip may have wrong bclk and lrclk output in master mode. then there
will be no sound.
With the pllprescale=1, postscale=2, the output clock is correct. so use
this configuration to workaround this issue.
Tested 8k/11k/16k/22k/32k/44k/48kHz case.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 7065943831d25ed55f9a789dacdd33b7a5ea18f7)
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/codecs/wm8960.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index 00ca1036bdd3..e218041796e5 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -1024,11 +1024,6 @@ static bool is_pll_freq_available(unsigned int source, unsigned int target) target *= 4; Ndiv = target / source; - if (Ndiv < 6) { - source >>= 1; - Ndiv = target / source; - } - if ((Ndiv < 6) || (Ndiv > 12)) return false; @@ -1139,6 +1134,9 @@ static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, if (pll_id == WM8960_SYSCLK_AUTO) return 0; + if (is_pll_freq_available(freq_in, freq_out)) + return -EINVAL; + return wm8960_set_pll(codec, freq_in, freq_out); } |