diff options
| -rw-r--r-- | arch/arm/configs/spitz_defconfig | 19 | ||||
| -rw-r--r-- | arch/arm/mach-ixp4xx/ixdp425-setup.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/mm/flush.c | 7 | ||||
| -rw-r--r-- | include/asm-arm/semaphore.h | 5 | ||||
| -rw-r--r-- | include/asm-arm/spinlock.h | 26 |
6 files changed, 51 insertions, 10 deletions
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig index 18e9beaec465..9895539533d6 100644 --- a/arch/arm/configs/spitz_defconfig +++ b/arch/arm/configs/spitz_defconfig @@ -897,7 +897,24 @@ CONFIG_UNIX98_PTYS=y # # I2C support # -# CONFIG_I2C is not set +CONFIG_I2C=y +# CONFIG_I2C_CHARDEV is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +CONFIG_I2C_PXA=y +# CONFIG_I2C_PXA_SLAVE is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_PCA_ISA is not set # # Hardware Monitoring support diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index 0a41080d2266..3a22d84e1047 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -85,7 +85,7 @@ static struct plat_serial8250_port ixdp425_uart_data[] = { { .mapbase = IXP4XX_UART2_BASE_PHYS, .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, - .irq = IRQ_IXP4XX_UART1, + .irq = IRQ_IXP4XX_UART2, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, .iotype = UPIO_MEM, .regshift = 2, diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 526acbc32067..2a58499c0968 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -77,6 +77,8 @@ config MACH_AKITA depends PXA_SHARPSL_27x select PXA_SHARP_Cxx00 select MACH_SPITZ + select I2C + select I2C_PXA config MACH_SPITZ bool "Enable Sharp Zaurus SL-3000 (Spitz) Support" diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index c9a03981b785..330695b6b19d 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -155,14 +155,19 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p * space mappings, we can be lazy and remember that we may have dirty * kernel cache lines for later. Otherwise, we assume we have * aliasing mappings. + * + * Note that we disable the lazy flush for SMP. */ void flush_dcache_page(struct page *page) { struct address_space *mapping = page_mapping(page); +#ifndef CONFIG_SMP if (mapping && !mapping_mapped(mapping)) set_bit(PG_dcache_dirty, &page->flags); - else { + else +#endif + { __flush_dcache_page(mapping, page); if (mapping && cache_is_vivt()) __flush_dcache_aliases(mapping, page); diff --git a/include/asm-arm/semaphore.h b/include/asm-arm/semaphore.h index 71ca7d412687..d5dc624f452a 100644 --- a/include/asm-arm/semaphore.h +++ b/include/asm-arm/semaphore.h @@ -47,11 +47,6 @@ static inline void init_MUTEX_LOCKED(struct semaphore *sem) sema_init(sem, 0); } -static inline int sema_count(struct semaphore *sem) -{ - return atomic_read(&sem->count); -} - /* * special register calling convention */ diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h index 6ed4f916b166..43ad4e55878c 100644 --- a/include/asm-arm/spinlock.h +++ b/include/asm-arm/spinlock.h @@ -30,6 +30,9 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) __asm__ __volatile__( "1: ldrex %0, [%1]\n" " teq %0, #0\n" +#ifdef CONFIG_CPU_32v6K +" wfene\n" +#endif " strexeq %0, %2, [%1]\n" " teqeq %0, #0\n" " bne 1b" @@ -65,7 +68,11 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock) smp_mb(); __asm__ __volatile__( -" str %1, [%0]" +" str %1, [%0]\n" +#ifdef CONFIG_CPU_32v6K +" mcr p15, 0, %1, c7, c10, 4\n" /* DSB */ +" sev" +#endif : : "r" (&lock->lock), "r" (0) : "cc"); @@ -87,6 +94,9 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) __asm__ __volatile__( "1: ldrex %0, [%1]\n" " teq %0, #0\n" +#ifdef CONFIG_CPU_32v6K +" wfene\n" +#endif " strexeq %0, %2, [%1]\n" " teq %0, #0\n" " bne 1b" @@ -122,7 +132,11 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw) smp_mb(); __asm__ __volatile__( - "str %1, [%0]" + "str %1, [%0]\n" +#ifdef CONFIG_CPU_32v6K +" mcr p15, 0, %1, c7, c10, 4\n" /* DSB */ +" sev\n" +#endif : : "r" (&rw->lock), "r" (0) : "cc"); @@ -148,6 +162,9 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) "1: ldrex %0, [%2]\n" " adds %0, %0, #1\n" " strexpl %1, %0, [%2]\n" +#ifdef CONFIG_CPU_32v6K +" wfemi\n" +#endif " rsbpls %0, %1, #0\n" " bmi 1b" : "=&r" (tmp), "=&r" (tmp2) @@ -169,6 +186,11 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw) " strex %1, %0, [%2]\n" " teq %1, #0\n" " bne 1b" +#ifdef CONFIG_CPU_32v6K +"\n cmp %0, #0\n" +" mcreq p15, 0, %0, c7, c10, 4\n" +" seveq" +#endif : "=&r" (tmp), "=&r" (tmp2) : "r" (&rw->lock) : "cc"); |