diff options
| -rw-r--r-- | arch/arm/configs/at91rm9200dk_defconfig | 1 | ||||
| -rw-r--r-- | arch/arm/configs/at91rm9200ek_defconfig | 1 | ||||
| -rw-r--r-- | arch/arm/configs/csb337_defconfig | 1 | ||||
| -rw-r--r-- | arch/arm/configs/csb637_defconfig | 1 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/pxa27x.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-s3c2410/Makefile | 5 | ||||
| -rw-r--r-- | arch/arm/mach-s3c2410/cpu.c | 18 | ||||
| -rw-r--r-- | arch/arm/mach-s3c2410/gpio.c | 72 | ||||
| -rw-r--r-- | arch/arm/mach-s3c2410/s3c2400-gpio.c | 45 | ||||
| -rw-r--r-- | arch/arm/mach-s3c2410/s3c2410-gpio.c | 93 | ||||
| -rw-r--r-- | arch/arm/mach-s3c2410/sleep.S | 2 | ||||
| -rw-r--r-- | arch/arm/mm/cache-v6.S | 18 | ||||
| -rw-r--r-- | arch/arm/mm/proc-xscale.S | 16 | ||||
| -rw-r--r-- | arch/arm/oprofile/common.c | 5 | ||||
| -rw-r--r-- | include/asm-arm/arch-s3c2410/hardware.h | 7 | ||||
| -rw-r--r-- | include/asm-arm/arch-s3c2410/regs-gpio.h | 22 | ||||
| -rw-r--r-- | include/asm-arm/checksum.h | 2 | ||||
| -rw-r--r-- | sound/arm/aaci.c | 14 |
18 files changed, 229 insertions, 96 deletions
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig index 5cdd13acf8ff..1fe73d198888 100644 --- a/arch/arm/configs/at91rm9200dk_defconfig +++ b/arch/arm/configs/at91rm9200dk_defconfig @@ -85,7 +85,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_CAMELOT is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_IOP3XX is not set diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig index 20838ccf1da7..b7d934cdb1b7 100644 --- a/arch/arm/configs/at91rm9200ek_defconfig +++ b/arch/arm/configs/at91rm9200ek_defconfig @@ -85,7 +85,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_CAMELOT is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_IOP3XX is not set diff --git a/arch/arm/configs/csb337_defconfig b/arch/arm/configs/csb337_defconfig index 885a3184830a..94bd9932a402 100644 --- a/arch/arm/configs/csb337_defconfig +++ b/arch/arm/configs/csb337_defconfig @@ -85,7 +85,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_CAMELOT is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_IOP3XX is not set diff --git a/arch/arm/configs/csb637_defconfig b/arch/arm/configs/csb637_defconfig index 95a96a5462a0..1519124c5501 100644 --- a/arch/arm/configs/csb637_defconfig +++ b/arch/arm/configs/csb637_defconfig @@ -85,7 +85,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_CAMELOT is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_IOP3XX is not set diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index b41b1efaa2cf..3baa70819f24 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -44,7 +44,7 @@ unsigned int get_clk_frequency_khz( int info) /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); - t = clkcfg & (1 << 1); + t = clkcfg & (1 << 0); ht = clkcfg & (1 << 2); b = clkcfg & (1 << 3); diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index b4f1e051c768..1217bf00309c 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -10,9 +10,13 @@ obj-m := obj-n := obj- := +# S3C2400 support files +obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o + # S3C2410 support files obj-$(CONFIG_CPU_S3C2410) += s3c2410.o +obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o obj-$(CONFIG_S3C2410_DMA) += dma.o # Power Management support @@ -25,6 +29,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o +obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o # bast extras diff --git a/arch/arm/mach-s3c2410/cpu.c b/arch/arm/mach-s3c2410/cpu.c index 687fe371369d..00a379334b60 100644 --- a/arch/arm/mach-s3c2410/cpu.c +++ b/arch/arm/mach-s3c2410/cpu.c @@ -40,6 +40,7 @@ #include "cpu.h" #include "clock.h" +#include "s3c2400.h" #include "s3c2410.h" #include "s3c2440.h" @@ -55,6 +56,7 @@ struct cpu_table { /* table of supported CPUs */ +static const char name_s3c2400[] = "S3C2400"; static const char name_s3c2410[] = "S3C2410"; static const char name_s3c2440[] = "S3C2440"; static const char name_s3c2410a[] = "S3C2410A"; @@ -96,7 +98,16 @@ static struct cpu_table cpu_ids[] __initdata = { .init_uarts = s3c2440_init_uarts, .init = s3c2440_init, .name = name_s3c2440a - } + }, + { + .idcode = 0x0, /* S3C2400 doesn't have an idcode */ + .idmask = 0xffffffff, + .map_io = s3c2400_map_io, + .init_clocks = s3c2400_init_clocks, + .init_uarts = s3c2400_init_uarts, + .init = s3c2400_init, + .name = name_s3c2400 + }, }; /* minimal IO mapping */ @@ -148,12 +159,15 @@ static struct cpu_table *cpu; void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) { - unsigned long idcode; + unsigned long idcode = 0x0; /* initialise the io descriptors we need for initialisation */ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); +#ifndef CONFIG_CPU_S3C2400 idcode = __raw_readl(S3C2410_GSTATUS1); +#endif + cpu = s3c_lookup_cpu(idcode); if (cpu == NULL) { diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c index 23ea3d5fa09c..cd39e8684584 100644 --- a/arch/arm/mach-s3c2410/gpio.c +++ b/arch/arm/mach-s3c2410/gpio.c @@ -31,6 +31,7 @@ * 05-Nov-2004 BJD EXPORT_SYMBOL() added for all code * 13-Mar-2005 BJD Updates for __iomem * 26-Oct-2005 BJD Added generic configuration types + * 15-Jan-2006 LCVR Added support for the S3C2400 */ @@ -48,7 +49,7 @@ void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function) { - void __iomem *base = S3C2410_GPIO_BASE(pin); + void __iomem *base = S3C24XX_GPIO_BASE(pin); unsigned long mask; unsigned long con; unsigned long flags; @@ -95,7 +96,7 @@ EXPORT_SYMBOL(s3c2410_gpio_cfgpin); unsigned int s3c2410_gpio_getcfg(unsigned int pin) { - void __iomem *base = S3C2410_GPIO_BASE(pin); + void __iomem *base = S3C24XX_GPIO_BASE(pin); unsigned long mask; if (pin < S3C2410_GPIO_BANKB) { @@ -111,7 +112,7 @@ EXPORT_SYMBOL(s3c2410_gpio_getcfg); void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) { - void __iomem *base = S3C2410_GPIO_BASE(pin); + void __iomem *base = S3C24XX_GPIO_BASE(pin); unsigned long offs = S3C2410_GPIO_OFFSET(pin); unsigned long flags; unsigned long up; @@ -133,7 +134,7 @@ EXPORT_SYMBOL(s3c2410_gpio_pullup); void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) { - void __iomem *base = S3C2410_GPIO_BASE(pin); + void __iomem *base = S3C24XX_GPIO_BASE(pin); unsigned long offs = S3C2410_GPIO_OFFSET(pin); unsigned long flags; unsigned long dat; @@ -152,7 +153,7 @@ EXPORT_SYMBOL(s3c2410_gpio_setpin); unsigned int s3c2410_gpio_getpin(unsigned int pin) { - void __iomem *base = S3C2410_GPIO_BASE(pin); + void __iomem *base = S3C24XX_GPIO_BASE(pin); unsigned long offs = S3C2410_GPIO_OFFSET(pin); return __raw_readl(base + 0x04) & (1<< offs); @@ -166,70 +167,13 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) unsigned long misccr; local_irq_save(flags); - misccr = __raw_readl(S3C2410_MISCCR); + misccr = __raw_readl(S3C24XX_MISCCR); misccr &= ~clear; misccr ^= change; - __raw_writel(misccr, S3C2410_MISCCR); + __raw_writel(misccr, S3C24XX_MISCCR); local_irq_restore(flags); return misccr; } EXPORT_SYMBOL(s3c2410_modify_misccr); - -int s3c2410_gpio_getirq(unsigned int pin) -{ - if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15_EINT23) - return -1; /* not valid interrupts */ - - if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7) - return -1; /* not valid pin */ - - if (pin < S3C2410_GPF4) - return (pin - S3C2410_GPF0) + IRQ_EINT0; - - if (pin < S3C2410_GPG0) - return (pin - S3C2410_GPF4) + IRQ_EINT4; - - return (pin - S3C2410_GPG0) + IRQ_EINT8; -} - -EXPORT_SYMBOL(s3c2410_gpio_getirq); - -int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, - unsigned int config) -{ - void __iomem *reg = S3C2410_EINFLT0; - unsigned long flags; - unsigned long val; - - if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15) - return -1; - - config &= 0xff; - - pin -= S3C2410_GPG8_EINT16; - reg += pin & ~3; - - local_irq_save(flags); - - /* update filter width and clock source */ - - val = __raw_readl(reg); - val &= ~(0xff << ((pin & 3) * 8)); - val |= config << ((pin & 3) * 8); - __raw_writel(val, reg); - - /* update filter enable */ - - val = __raw_readl(S3C2410_EXTINT2); - val &= ~(1 << ((pin * 4) + 3)); - val |= on << ((pin * 4) + 3); - __raw_writel(val, S3C2410_EXTINT2); - - local_irq_restore(flags); - - return 0; -} - -EXPORT_SYMBOL(s3c2410_gpio_irqfilter); diff --git a/arch/arm/mach-s3c2410/s3c2400-gpio.c b/arch/arm/mach-s3c2410/s3c2400-gpio.c new file mode 100644 index 000000000000..5127f39fa9bf --- /dev/null +++ b/arch/arm/mach-s3c2410/s3c2400-gpio.c @@ -0,0 +1,45 @@ +/* linux/arch/arm/mach-s3c2410/gpio.c + * + * Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org> + * + * S3C2400 GPIO support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Changelog + * 15-Jan-2006 LCVR Splitted from gpio.c, adding support for the S3C2400 + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> + +#include <asm/hardware.h> +#include <asm/irq.h> +#include <asm/io.h> + +#include <asm/arch/regs-gpio.h> + +int s3c2400_gpio_getirq(unsigned int pin) +{ + if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7) + return -1; /* not valid interrupts */ + + return (pin - S3C2410_GPE0) + IRQ_EINT0; +} + +EXPORT_SYMBOL(s3c2400_gpio_getirq); diff --git a/arch/arm/mach-s3c2410/s3c2410-gpio.c b/arch/arm/mach-s3c2410/s3c2410-gpio.c new file mode 100644 index 000000000000..d5e1caea1d23 --- /dev/null +++ b/arch/arm/mach-s3c2410/s3c2410-gpio.c @@ -0,0 +1,93 @@ +/* linux/arch/arm/mach-s3c2410/gpio.c + * + * Copyright (c) 2004-2006 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C2410 GPIO support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Changelog + * 15-Jan-2006 LCVR Splitted from gpio.c + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> + +#include <asm/hardware.h> +#include <asm/irq.h> +#include <asm/io.h> + +#include <asm/arch/regs-gpio.h> + +int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, + unsigned int config) +{ + void __iomem *reg = S3C2410_EINFLT0; + unsigned long flags; + unsigned long val; + + if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15) + return -1; + + config &= 0xff; + + pin -= S3C2410_GPG8_EINT16; + reg += pin & ~3; + + local_irq_save(flags); + + /* update filter width and clock source */ + + val = __raw_readl(reg); + val &= ~(0xff << ((pin & 3) * 8)); + val |= config << ((pin & 3) * 8); + __raw_writel(val, reg); + + /* update filter enable */ + + val = __raw_readl(S3C2410_EXTINT2); + val &= ~(1 << ((pin * 4) + 3)); + val |= on << ((pin * 4) + 3); + __raw_writel(val, S3C2410_EXTINT2); + + local_irq_restore(flags); + + return 0; +} + +EXPORT_SYMBOL(s3c2410_gpio_irqfilter); + +int s3c2410_gpio_getirq(unsigned int pin) +{ + if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15_EINT23) + return -1; /* not valid interrupts */ + + if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7) + return -1; /* not valid pin */ + + if (pin < S3C2410_GPF4) + return (pin - S3C2410_GPF0) + IRQ_EINT0; + + if (pin < S3C2410_GPG0) + return (pin - S3C2410_GPF4) + IRQ_EINT4; + + return (pin - S3C2410_GPG0) + IRQ_EINT8; +} + +EXPORT_SYMBOL(s3c2410_gpio_getirq); diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S index e9a055b779b7..832fb86a03b4 100644 --- a/arch/arm/mach-s3c2410/sleep.S +++ b/arch/arm/mach-s3c2410/sleep.S @@ -72,7 +72,7 @@ ENTRY(s3c2410_cpu_suspend) @@ prepare cpu to sleep ldr r4, =S3C2410_REFRESH - ldr r5, =S3C2410_MISCCR + ldr r5, =S3C24XX_MISCCR ldr r6, =S3C2410_CLKCON ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB) ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB) diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 72966d90e956..d921c1024ae0 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -92,22 +92,16 @@ ENTRY(v6_coherent_kern_range) * - the Icache does not read data from the write buffer */ ENTRY(v6_coherent_user_range) - bic r0, r0, #CACHE_LINE_SIZE - 1 -1: + #ifdef HARVARD_CACHE - mcr p15, 0, r0, c7, c10, 1 @ clean D line + bic r0, r0, #CACHE_LINE_SIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D line mcr p15, 0, r0, c7, c5, 1 @ invalidate I line -#endif - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE + add r0, r0, #CACHE_LINE_SIZE cmp r0, r1 blo 1b +#endif + mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB #ifdef HARVARD_CACHE mov r0, #0 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 861b35947280..2d3823ec3153 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -241,7 +241,15 @@ ENTRY(xscale_flush_user_cache_range) * it also trashes the mini I-cache used by JTAG debuggers. */ ENTRY(xscale_coherent_kern_range) - /* FALLTHROUGH */ + bic r0, r0, #CACHELINESIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #CACHELINESIZE + cmp r0, r1 + blo 1b + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB + mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr /* * coherent_user_range(start, end) @@ -252,18 +260,16 @@ ENTRY(xscale_coherent_kern_range) * * - start - virtual start address * - end - virtual end address - * - * Note: single I-cache line invalidation isn't used here since - * it also trashes the mini I-cache used by JTAG debuggers. */ ENTRY(xscale_coherent_user_range) bic r0, r0, #CACHELINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry add r0, r0, #CACHELINESIZE cmp r0, r1 blo 1b mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB + mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer mov pc, lr diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c index 1415930ceee1..6f8bc1f0e6a1 100644 --- a/arch/arm/oprofile/common.c +++ b/arch/arm/oprofile/common.c @@ -137,8 +137,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) if (spec) { init_MUTEX(&op_arm_sem); - if (spec->init() < 0) - return -ENODEV; + ret = spec->init(); + if (ret < 0) + return ret; op_arm_model = spec; init_driverfs(); diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h index 1c9de29cafef..a2330bf83695 100644 --- a/include/asm-arm/arch-s3c2410/hardware.h +++ b/include/asm-arm/arch-s3c2410/hardware.h @@ -17,6 +17,7 @@ * 14-Sep-2004 BJD Added misccr and getpin to gpio * 01-Oct-2004 BJD Added the new gpio functions * 16-Oct-2004 BJD Removed the clock variables + * 15-Jan-2006 LCVR Added s3c2400_gpio_getirq() */ #ifndef __ASM_ARCH_HARDWARE_H @@ -55,6 +56,12 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); extern int s3c2410_gpio_getirq(unsigned int pin); +#ifdef CONFIG_CPU_S3C2400 + +extern int s3c2400_gpio_getirq(unsigned int pin); + +#endif /* CONFIG_CPU_S3C2400 */ + /* s3c2410_gpio_irqfilter * * set the irq filtering on the given pin diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index 7f1be48ad67e..9697f93afe74 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h @@ -22,6 +22,7 @@ * 28-Mar-2005 LCVR Fixed definition of GPB10 * 26-Oct-2005 BJD Added generic configuration types * 27-Nov-2005 LCVR Added definitions to S3C2400 registers + * 15-Jan-2006 LCVR Written S3C24XX_GPIO_BASE() macro */ @@ -39,6 +40,27 @@ #define S3C2410_GPIO_BANKG (32*6) #define S3C2410_GPIO_BANKH (32*7) +#ifdef CONFIG_CPU_S3C2400 +#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) +#define S3C24XX_MISCCR S3C2400_MISCCR +#else +#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) +#define S3C24XX_MISCCR S3C2410_MISCCR +#endif /* CONFIG_CPU_S3C2400 */ + + +/* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */ + +#define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32) +#define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2)) +#define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \ + (2 * (S3C2400_BANKNUM(pin)-2))) + +#define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \ + S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \ + S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO) + + #define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO) #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31) diff --git a/include/asm-arm/checksum.h b/include/asm-arm/checksum.h index d4256d5f3a7c..747bdd31a74b 100644 --- a/include/asm-arm/checksum.h +++ b/include/asm-arm/checksum.h @@ -77,7 +77,7 @@ ip_fast_csum(unsigned char * iph, unsigned int ihl) mov %0, %0, lsr #16" : "=r" (sum), "=r" (iph), "=r" (ihl), "=r" (tmp1) : "1" (iph), "2" (ihl) - : "cc"); + : "cc", "memory"); return sum; } diff --git a/sound/arm/aaci.c b/sound/arm/aaci.c index 54147c1f6361..149feb410654 100644 --- a/sound/arm/aaci.c +++ b/sound/arm/aaci.c @@ -882,14 +882,20 @@ static int __devinit aaci_probe(struct amba_device *dev, void *id) writel(0x1fff, aaci->base + AACI_INTCLR); writel(aaci->maincr, aaci->base + AACI_MAINCR); + ret = aaci_probe_ac97(aaci); + if (ret) + goto out; + /* - * Size the FIFOs. + * Size the FIFOs (must be multiple of 16). */ aaci->fifosize = aaci_size_fifo(aaci); - - ret = aaci_probe_ac97(aaci); - if (ret) + if (aaci->fifosize & 15) { + printk(KERN_WARNING "AACI: fifosize = %d not supported\n", + aaci->fifosize); + ret = -ENODEV; goto out; + } ret = aaci_init_pcm(aaci); if (ret) |