diff options
| -rw-r--r-- | arch/arm/mach-realview/platsmp.c | 43 | ||||
| -rw-r--r-- | arch/arm/mm/proc-v6.S | 14 | ||||
| -rw-r--r-- | include/asm-arm/arch-realview/scu.h | 11 | ||||
| -rw-r--r-- | include/asm-arm/hardware/arm_scu.h | 15 |
4 files changed, 43 insertions, 40 deletions
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index de2b7159557d..2ff1acaf2be7 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -15,11 +15,13 @@ #include <linux/smp.h> #include <asm/cacheflush.h> -#include <asm/hardware/arm_scu.h> #include <asm/hardware.h> #include <asm/io.h> #include <asm/mach-types.h> +#include <asm/arch/board-eb.h> +#include <asm/arch/scu.h> + extern void realview_secondary_startup(void); /* @@ -31,9 +33,13 @@ volatile int __cpuinitdata pen_release = -1; static unsigned int __init get_core_count(void) { unsigned int ncores; + void __iomem *scu_base = 0; + + if (machine_is_realview_eb() && core_tile_eb11mp()) + scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); - if (machine_is_realview_eb() && core_tile_eb11mp()) { - ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG); + if (scu_base) { + ncores = __raw_readl(scu_base + SCU_CONFIG); ncores = (ncores & 0x03) + 1; } else ncores = 1; @@ -41,6 +47,24 @@ static unsigned int __init get_core_count(void) return ncores; } +/* + * Setup the SCU + */ +static void scu_enable(void) +{ + u32 scu_ctrl; + void __iomem *scu_base; + + if (machine_is_realview_eb() && core_tile_eb11mp()) + scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); + else + BUG(); + + scu_ctrl = __raw_readl(scu_base + SCU_CTRL); + scu_ctrl |= 1; + __raw_writel(scu_ctrl, scu_base + SCU_CTRL); +} + static DEFINE_SPINLOCK(boot_lock); void __cpuinit platform_secondary_init(unsigned int cpu) @@ -210,11 +234,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus) cpu_set(i, cpu_present_map); /* - * Do we need any more CPUs? If so, then let them know where - * to start. Note that, on modern versions of MILO, the "poke" - * doesn't actually do anything until each individual core is - * sent a soft interrupt to get it out of WFI + * Initialise the SCU if there are more than one CPU and let + * them know where to start. Note that, on modern versions of + * MILO, the "poke" doesn't actually do anything until each + * individual core is sent a soft interrupt to get it out of + * WFI */ - if (max_cpus > 1) + if (max_cpus > 1) { + scu_enable(); poke_milo(); + } } diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 2162a692d99a..bf760ea2f789 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -17,10 +17,6 @@ #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> -#ifdef CONFIG_SMP -#include <asm/hardware/arm_scu.h> -#endif - #include "proc-macros.S" #define D_CACHE_LINE_SIZE 32 @@ -187,20 +183,10 @@ cpu_v6_name: */ __v6_setup: #ifdef CONFIG_SMP - /* Set up the SCU on core 0 only */ - mrc p15, 0, r0, c0, c0, 5 @ CPU core number - ands r0, r0, #15 - ldreq r0, =SCU_BASE - ldreq r5, [r0, #SCU_CTRL] - orreq r5, r5, #1 - streq r5, [r0, #SCU_CTRL] - -#ifndef CONFIG_CPU_DCACHE_DISABLE mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode orr r0, r0, #0x20 mcr p15, 0, r0, c1, c0, 1 #endif -#endif mov r0, #0 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h index 08b3db883c36..d55802d645af 100644 --- a/include/asm-arm/arch-realview/scu.h +++ b/include/asm-arm/arch-realview/scu.h @@ -1,8 +1,13 @@ #ifndef __ASMARM_ARCH_SCU_H #define __ASMARM_ARCH_SCU_H -#include <asm/arch/board-eb.h> - -#define SCU_BASE REALVIEW_EB11MP_SCU_BASE +/* + * SCU registers + */ +#define SCU_CTRL 0x00 +#define SCU_CONFIG 0x04 +#define SCU_CPU_STATUS 0x08 +#define SCU_INVALIDATE 0x0c +#define SCU_FPGA_REVISION 0x10 #endif diff --git a/include/asm-arm/hardware/arm_scu.h b/include/asm-arm/hardware/arm_scu.h deleted file mode 100644 index 7d28eb5a1758..000000000000 --- a/include/asm-arm/hardware/arm_scu.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef ASMARM_HARDWARE_ARM_SCU_H -#define ASMARM_HARDWARE_ARM_SCU_H - -#include <asm/arch/scu.h> - -/* - * SCU registers - */ -#define SCU_CTRL 0x00 -#define SCU_CONFIG 0x04 -#define SCU_CPU_STATUS 0x08 -#define SCU_INVALIDATE 0x0c -#define SCU_FPGA_REVISION 0x10 - -#endif |