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-rw-r--r--arch/arm/mach-tegra/board-ardbeg-memory.c3
-rw-r--r--arch/arm/mach-tegra/board-ardbeg-sensors.c34
-rw-r--r--arch/arm/mach-tegra/board-ardbeg.c1
-rw-r--r--arch/arm/mach-tegra/board-loki-memory.c65
-rw-r--r--arch/arm/mach-tegra/board-loki-panel.c4
-rw-r--r--arch/arm/mach-tegra/board-loki-power.c7
-rw-r--r--arch/arm/mach-tegra/board-panel.h1
-rw-r--r--arch/arm/mach-tegra/cpuidle.c4
-rw-r--r--arch/arm/mach-tegra/include/mach/dc.h2
-rw-r--r--arch/arm/mach-tegra/mc.c6
-rw-r--r--arch/arm/mach-tegra/pm.c9
-rw-r--r--arch/arm/mach-tegra/pm_domains.c56
-rw-r--r--arch/arm/mach-tegra/tegra12_emc.c5
13 files changed, 16 insertions, 181 deletions
diff --git a/arch/arm/mach-tegra/board-ardbeg-memory.c b/arch/arm/mach-tegra/board-ardbeg-memory.c
index 7c15bca409e0..376e185a13f0 100644
--- a/arch/arm/mach-tegra/board-ardbeg-memory.c
+++ b/arch/arm/mach-tegra/board-ardbeg-memory.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -5429,7 +5429,6 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200020, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1180, /* expected dvfs latency (ns) */
},
};
diff --git a/arch/arm/mach-tegra/board-ardbeg-sensors.c b/arch/arm/mach-tegra/board-ardbeg-sensors.c
index 4591beb9ee0a..a52e6e47a134 100644
--- a/arch/arm/mach-tegra/board-ardbeg-sensors.c
+++ b/arch/arm/mach-tegra/board-ardbeg-sensors.c
@@ -534,35 +534,6 @@ static struct dw9718_platform_data ardbeg_dw9718_data = {
.detect = ardbeg_dw9718_detect,
};
-static struct max77387_platform_data ardbeg_max77387_pdata = {
- .config = {
- .led_mask = 3,
- .flash_trigger_mode = 1,
- /* use ONE-SHOOT flash mode - flash triggered at the
- * raising edge of strobe or strobe signal.
- */
- .flash_mode = 1,
- .def_ftimer = 0x24,
- .max_total_current_mA = 1000,
- .max_peak_current_mA = 600,
- .led_config[0] = {
- .flash_torch_ratio = 18100,
- .granularity = 1000,
- .flash_levels = 0,
- .lumi_levels = NULL,
- },
- .led_config[1] = {
- .flash_torch_ratio = 18100,
- .granularity = 1000,
- .flash_levels = 0,
- .lumi_levels = NULL,
- },
- },
- .cfg = 0,
- .dev_name = "torch",
- .gpio_strobe = CAM_FLASH_STROBE,
-};
-
static struct as364x_platform_data ardbeg_as3648_data = {
.config = {
.led_mask = 3,
@@ -870,11 +841,6 @@ static struct i2c_board_info ardbeg_i2c_board_info_as3648 = {
.platform_data = &ardbeg_as3648_data,
};
-static struct i2c_board_info ardbeg_i2c_board_info_max77387 = {
- I2C_BOARD_INFO("max77387", 0x4A),
- .platform_data = &ardbeg_max77387_pdata,
-};
-
static struct camera_module ardbeg_camera_module_info[] = {
/* E1823 camera board */
{
diff --git a/arch/arm/mach-tegra/board-ardbeg.c b/arch/arm/mach-tegra/board-ardbeg.c
index e5738bedc61b..c6d089e2b55c 100644
--- a/arch/arm/mach-tegra/board-ardbeg.c
+++ b/arch/arm/mach-tegra/board-ardbeg.c
@@ -946,7 +946,6 @@ static struct spi_board_info rm31080a_norrin_spi_board[1] = {
static int __init ardbeg_touch_init(void)
{
- struct board_info pmu_board_info;
tegra_get_board_info(&board_info);
if (tegra_get_touch_vendor_id() == MAXIM_TOUCH) {
diff --git a/arch/arm/mach-tegra/board-loki-memory.c b/arch/arm/mach-tegra/board-loki-memory.c
index 6e6dff92710b..1c20b03e4558 100644
--- a/arch/arm/mach-tegra/board-loki-memory.c
+++ b/arch/arm/mach-tegra/board-loki-memory.c
@@ -248,7 +248,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 57820, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -474,7 +473,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 35610, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -700,7 +698,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 20850, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -926,7 +923,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 10720, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -1152,7 +1148,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 6890, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -1378,7 +1373,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 3420, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -1604,7 +1598,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 2680, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -1830,7 +1823,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 2180, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -2056,7 +2048,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1440, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -2282,7 +2273,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200010, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1440, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -2508,7 +2498,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200018, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1200, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -2734,7 +2723,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200020, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1180, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -2960,7 +2948,6 @@ static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200028, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1180, /* expected dvfs latency (ns) */
},
};
@@ -3189,7 +3176,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 57820, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -3415,7 +3401,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 35610, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -3641,7 +3626,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 20850, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -3867,7 +3851,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 10720, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -4093,7 +4076,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 6890, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -4319,7 +4301,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 3420, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -4545,7 +4526,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 2680, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -4771,7 +4751,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 2180, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -4997,7 +4976,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1440, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -5223,7 +5201,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200010, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1440, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -5449,7 +5426,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200018, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1200, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -5675,7 +5651,6 @@ static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200020, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1180, /* expected dvfs latency (ns) */
},
};
@@ -5904,7 +5879,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 57820, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -6130,7 +6104,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 35610, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -6356,7 +6329,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 20850, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -6582,7 +6554,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 10720, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -6808,7 +6779,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 6890, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -7034,7 +7004,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 3420, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -7260,7 +7229,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 2680, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -7486,7 +7454,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 2180, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -7712,7 +7679,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1440, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -7938,7 +7904,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200010, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1440, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -8164,7 +8129,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200018, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1200, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -8390,7 +8354,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200020, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1180, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.6 */
@@ -8616,7 +8579,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200028, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1180, /* expected dvfs latency (ns) */
},
};
@@ -8845,7 +8807,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 57820, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -9071,7 +9032,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 35610, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -9297,7 +9257,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 20850, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -9523,7 +9482,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 10720, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -9749,7 +9707,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 6890, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -9975,7 +9932,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 3420, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -10201,7 +10157,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 2680, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -10427,7 +10382,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 2180, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -10653,7 +10607,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1440, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -10879,7 +10832,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200010, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1440, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -11105,7 +11057,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200018, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1200, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -11331,7 +11282,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200020, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1180, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -11557,7 +11507,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200028, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1180, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -11783,7 +11732,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200028, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1180, /* expected dvfs latency (ns) */
},
};
@@ -12012,7 +11960,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 57820, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -12238,7 +12185,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 35610, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -12464,7 +12410,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 20850, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -12690,7 +12635,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 10720, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -12916,7 +12860,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 6890, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -13142,7 +13085,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 3420, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -13368,7 +13310,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 2680, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -13594,7 +13535,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 2180, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -13820,7 +13760,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1440, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -14046,7 +13985,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200010, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1440, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -14272,7 +14210,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200018, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1200, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -14498,7 +14435,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200020, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1180, /* expected dvfs latency (ns) */
},
{
0x18, /* V5.0.9 */
@@ -14724,7 +14660,6 @@ static struct tegra12_emc_table loki_ffd_sku100_emc_table[] = {
0x80100002, /* Mode Register 1 */
0x80200028, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
- 1180, /* expected dvfs latency (ns) */
},
};
diff --git a/arch/arm/mach-tegra/board-loki-panel.c b/arch/arm/mach-tegra/board-loki-panel.c
index 8e868c7373db..dc0b1ac1e89b 100644
--- a/arch/arm/mach-tegra/board-loki-panel.c
+++ b/arch/arm/mach-tegra/board-loki-panel.c
@@ -1,7 +1,7 @@
/*
* arch/arm/mach-tegra/board-loki-panel.c
*
- * Copyright (c) 2011-2013, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2011-2014, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -210,7 +210,7 @@ static int loki_hdmi_hotplug_init(struct device *dev)
__func__, PTR_ERR(loki_hdmi_vddio));
loki_hdmi_vddio = NULL;
} else
- regulator_enable(loki_hdmi_vddio);
+ return regulator_enable(loki_hdmi_vddio);
}
return 0;
}
diff --git a/arch/arm/mach-tegra/board-loki-power.c b/arch/arm/mach-tegra/board-loki-power.c
index 46f7174e5b7b..eb758498d82a 100644
--- a/arch/arm/mach-tegra/board-loki-power.c
+++ b/arch/arm/mach-tegra/board-loki-power.c
@@ -364,13 +364,6 @@ static struct palmas_reg_init *loki_reg_init[PALMAS_NUM_REGS] = {
NULL,
};
-#define PALMAS_GPADC_IIO_MAP(_ch, _dev_name, _name) \
- { \
- .adc_channel_label = PALMAS_DATASHEET_NAME(_ch),\
- .consumer_dev_name = _dev_name, \
- .consumer_channel = _name, \
- }
-
static struct iio_map palmas_adc_iio_maps[] = {
PALMAS_GPADC_IIO_MAP(IN1, "generic-adc-thermal.0", "thermistor"),
PALMAS_GPADC_IIO_MAP(IN3, "generic-adc-thermal.1", "tdiode"),
diff --git a/arch/arm/mach-tegra/board-panel.h b/arch/arm/mach-tegra/board-panel.h
index 8e16fab4f549..7e334934c015 100644
--- a/arch/arm/mach-tegra/board-panel.h
+++ b/arch/arm/mach-tegra/board-panel.h
@@ -20,6 +20,7 @@
#define __MACH_TEGRA_BOARD_PANEL_H
#include <linux/platform_device.h>
+#include <mach/dc.h>
#include "tegra-board-id.h"
struct tegra_panel {
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index e515c5b1ac96..6c0aadc75d4d 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -3,7 +3,7 @@
*
* CPU idle driver for Tegra CPUs
*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011 Google, Inc.
* Author: Colin Cross <ccross@android.com>
* Gary King <gking@nvidia.com>
@@ -276,8 +276,6 @@ static int __init tegra_cpuidle_init(void)
{
unsigned int cpu;
int ret;
- struct cpuidle_driver *drv;
- struct cpuidle_state *state;
#ifdef CONFIG_PM_SLEEP
tegra_pd_min_residency = tegra_cpu_lp2_min_residency();
diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h
index 7a1d03a871c1..3a73f1e99bfb 100644
--- a/arch/arm/mach-tegra/include/mach/dc.h
+++ b/arch/arm/mach-tegra/include/mach/dc.h
@@ -280,7 +280,7 @@ struct tegra_dsi_out {
u16 dsi_panel_rst_gpio;
u16 dsi_panel_bl_en_gpio;
u16 dsi_panel_bl_pwm_gpio;
- u8 chip_id;
+ u16 chip_id;
u8 chip_rev;
u8 controller_vs;
diff --git a/arch/arm/mach-tegra/mc.c b/arch/arm/mach-tegra/mc.c
index 908a33bb0833..952a7b8caf90 100644
--- a/arch/arm/mach-tegra/mc.c
+++ b/arch/arm/mach-tegra/mc.c
@@ -2,7 +2,7 @@
* arch/arm/mach-tegra/mc.c
*
* Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011-2013, NVIDIA Corporation. All rights reserved.
+ * Copyright (C) 2011-2014, NVIDIA Corporation. All rights reserved.
*
* Author:
* Erik Gilling <konkers@google.com>
@@ -259,7 +259,11 @@ EXPORT_SYMBOL(tegra_mc_flush_done);
*/
static int __init tegra_mc_init(void)
{
+
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
+ defined(CONFIG_TEGRA_MC_EARLY_ACK)
u32 reg;
+#endif
struct dentry *mc_debugfs_dir;
tegra_mc_timing_save();
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 347848a8139f..51cc64fcfaaa 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -293,13 +293,6 @@ int tegra_unregister_pm_notifier(struct notifier_block *nb)
}
EXPORT_SYMBOL(tegra_unregister_pm_notifier);
-static int tegra_pm_notifier_call_chain(unsigned int val)
-{
- int ret = raw_notifier_call_chain(&tegra_pm_chain_head, val, NULL);
-
- return notifier_to_errno(ret);
-}
-
#ifdef CONFIG_PM_SLEEP
static const char *tegra_suspend_name[TEGRA_MAX_SUSPEND_MODE] = {
[TEGRA_SUSPEND_NONE] = "none",
@@ -1800,7 +1793,7 @@ void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
WARN_ON(!orig);
if (!orig) {
pr_err("%s: Failed to map tegra_lp0_vec_start %08x\n",
- __func__, tegra_lp0_vec_start);
+ __func__, (unsigned int) tegra_lp0_vec_start);
kfree(reloc_lp0);
goto out;
}
diff --git a/arch/arm/mach-tegra/pm_domains.c b/arch/arm/mach-tegra/pm_domains.c
index 76bdfe92af1c..6252b523cda7 100644
--- a/arch/arm/mach-tegra/pm_domains.c
+++ b/arch/arm/mach-tegra/pm_domains.c
@@ -1,7 +1,7 @@
/*
* arch/arm/mach-tegra/pm_domains.c
*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
*
*
* This software is licensed under the terms of the GNU General Public
@@ -175,60 +175,6 @@ static int tegra_mc_clk_power_on(struct generic_pm_domain *genpd)
return 0;
}
-static void suspend_devices_in_domain(struct generic_pm_domain *genpd)
-{
- struct pm_domain_data *pdd;
- struct device *dev;
-
- list_for_each_entry(pdd, &genpd->dev_list, list_node) {
- dev = pdd->dev;
-
- if (dev->pm_domain && dev->pm_domain->ops.suspend)
- dev->pm_domain->ops.suspend(dev);
- }
-}
-
-static void resume_devices_in_domain(struct generic_pm_domain *genpd)
-{
- struct pm_domain_data *pdd;
- struct device *dev;
-
- list_for_each_entry(pdd, &genpd->dev_list, list_node) {
- dev = pdd->dev;
-
- if (dev->pm_domain && dev->pm_domain->ops.resume)
- dev->pm_domain->ops.resume(dev);
- }
-}
-
-static int tegra_core_power_on(struct generic_pm_domain *genpd)
-{
- struct pm_domain_data *pdd;
- struct gpd_link *link;
-
- list_for_each_entry(link, &genpd->master_links, master_node)
- resume_devices_in_domain(link->slave);
-
- list_for_each_entry(pdd, &genpd->dev_list, list_node)
- TEGRA_PD_DEV_CALLBACK(resume, pdd->dev);
-
- return 0;
-}
-
-static int tegra_core_power_off(struct generic_pm_domain *genpd)
-{
- struct pm_domain_data *pdd;
- struct gpd_link *link;
-
- list_for_each_entry(link, &genpd->master_links, master_node)
- suspend_devices_in_domain(link->slave);
-
- list_for_each_entry(pdd, &genpd->dev_list, list_node)
- TEGRA_PD_DEV_CALLBACK(suspend, pdd->dev);
-
- return 0;
-}
-
static struct tegra_pm_domain tegra_nvavp = {
.gpd.name = "tegra_nvavp",
};
diff --git a/arch/arm/mach-tegra/tegra12_emc.c b/arch/arm/mach-tegra/tegra12_emc.c
index 23e2f2831fb5..e77adfde979a 100644
--- a/arch/arm/mach-tegra/tegra12_emc.c
+++ b/arch/arm/mach-tegra/tegra12_emc.c
@@ -1,7 +1,7 @@
/*
* arch/arm/mach-tegra/tegra12_emc.c
*
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -662,7 +662,8 @@ static noinline void emc_set_clock(const struct tegra12_emc_table *next_timing,
u32 clk_setting)
{
#ifndef EMULATE_CLOCK_SWITCH
- int i, dll_change, pre_wait, ctt_term_changed;
+ int i, dll_change, pre_wait;
+ int ctt_term_changed = 0;
bool cfg_pow_features_enabled, zcal_long;
u32 bgbias_ctl, auto_cal_status, auto_cal_config;
u32 emc_cfg_reg = emc_readl(EMC_CFG);
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-28 05:23:11 +0000