diff options
| -rw-r--r-- | arch/arm/mach-tegra/tegra12_clocks.c | 67 |
1 files changed, 35 insertions, 32 deletions
diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c index 2b1ee1cf3198..43f7d5f3a5a4 100644 --- a/arch/arm/mach-tegra/tegra12_clocks.c +++ b/arch/arm/mach-tegra/tegra12_clocks.c @@ -642,6 +642,7 @@ static unsigned long tegra12_clk_cap_shared_bus(struct clk *bus, unsigned long rate, unsigned long ceiling); static bool tegra12_periph_is_special_reset(struct clk *c); +static void tegra12_dfll_cpu_late_init(struct clk *c); static bool detach_shared_bus; module_param(detach_shared_bus, bool, 0644); @@ -4287,38 +4288,6 @@ static void tune_cpu_trimmers(bool trim_high) } #endif -static void __init tegra12_dfll_cpu_late_init(struct clk *c) -{ -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS - int ret; - struct clk *cpu = tegra_get_clock_by_name("cpu_g"); - - if (!cpu || !cpu->dvfs) { - pr_err("%s: CPU dvfs is not present\n", __func__); - return; - } - tegra_dvfs_set_dfll_tune_trimmers(cpu->dvfs, tune_cpu_trimmers); - - /* release dfll clock source reset, init cl_dvfs control logic, and - move dfll to initialized state, so it can be used as CPU source */ - tegra_periph_reset_deassert(c); - ret = tegra_init_cl_dvfs(); - if (!ret) { - c->state = OFF; - if (tegra_platform_is_silicon()) { - use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE; -#ifdef CONFIG_ARCH_TEGRA_13x_SOC - if (tegra_cpu_speedo_id() == 0) - use_dfll = 0; -#endif - } - tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll); - tegra_cl_dvfs_debug_init(c); - pr_info("Tegra CPU DFLL is initialized with use_dfll = %d\n", use_dfll); - } -#endif -} - static void __init tegra12_dfll_clk_init(struct clk *c) { c->ops->init = tegra12_dfll_cpu_late_init; @@ -8919,6 +8888,40 @@ static bool tegra12_is_dyn_ramp( return false; } +/* DFLL late init called with CPU clock lock taken */ +static void __init tegra12_dfll_cpu_late_init(struct clk *c) +{ +#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS + int ret; + struct clk *cpu = &tegra_clk_virtual_cpu_g; + + if (!cpu || !cpu->dvfs) { + pr_err("%s: CPU dvfs is not present\n", __func__); + return; + } + tegra_dvfs_set_dfll_tune_trimmers(cpu->dvfs, tune_cpu_trimmers); + + /* release dfll clock source reset, init cl_dvfs control logic, and + move dfll to initialized state, so it can be used as CPU source */ + tegra_periph_reset_deassert(c); + ret = tegra_init_cl_dvfs(); + if (!ret) { + c->state = OFF; + if (tegra_platform_is_silicon()) { + use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE; +#ifdef CONFIG_ARCH_TEGRA_13x_SOC + if (tegra_cpu_speedo_id() == 0) + use_dfll = 0; +#endif + } + tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll); + tegra_cl_dvfs_debug_init(c); + pr_info("Tegra CPU DFLL is initialized with use_dfll = %d\n", + use_dfll); + } +#endif +} + /* * Backup pll is used as transitional CPU clock source while main pll is * relocking; in addition all CPU rates below backup level are sourced from |