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-rw-r--r--Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt132
-rw-r--r--arch/arm/boot/dts/tegra124-tn8-emc.dtsi2010
-rw-r--r--arch/arm/boot/dts/tegra124-tn8-generic.dtsi3
-rw-r--r--arch/arm/mach-tegra/Makefile2
-rw-r--r--arch/arm/mach-tegra/board-ardbeg-memory.c9
-rw-r--r--arch/arm/mach-tegra/tegra11_emc.c252
-rw-r--r--arch/arm/mach-tegra/tegra12_emc.c16
-rw-r--r--arch/arm/mach-tegra/tegra_emc_dt_parse.c365
-rw-r--r--arch/arm/mach-tegra/tegra_emc_dt_parse.h27
9 files changed, 2564 insertions, 252 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt
index fb795bfaee2f..18967ccf0aa7 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt
@@ -265,3 +265,135 @@ optional properties:
nvidia,emc-mode-4 = <0>;
nvidia,emc-min-mv = <0>;
};
+
+Tables for Tegra124:
+
+Properties:
+- name : Should be emc-table
+- compatible : Should contain "nvidia,tegra12-emc-table".
+- reg : either an opaque enumerator to tell different tables apart, or
+ the valid frequency for which the table should be used (in kHz).
+- nvidia,revision : SDRAM revision.
+- nvidia,dvfs-version : DVFS table versionl.
+- clock-frequency : the clock frequency for the EMC at which this
+ table should be used (in kHz).
+- nvidia,emc-min-mv : Minimum voltage
+- nvidia,source : Source name.
+- nvidia,src-sel-reg : Source register settings.
+- nvidia, burst-regs-num : Number of emc-registers.
+- nvidia,burst-up-down-regs-num : Number of up_down_regs.
+- nvidia,emc-registers : a word array of EMC registers to be programmed.
+ for operation at the 'clock-frequency' setting.
+ The order and contents of the registers are:
+ RC, RFC, RFC_SLR, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD,
+ RRD, REXT, WEXT, WDV, WDV_MASK, QUSE, QUSE_WIDTH, IBDLY, EINPUT,
+ EINPUT_DURATION, PUTERM_EXTRA, PUTERM_WIDTH, PUTERM_ADJ, CDB_CNTL_1,
+ CDB_CNTL_2, CDB_CNTL_3, QRST, QSAFE, RDV, RDV_MASK, REFRESH,
+ BURST_REFRESH_NUM, PRE_REFRESH_REQ_CNT, PDEX2WR, PDEX2RD, PCHG2PDEN,
+ ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TXSRDLL, TCKE, TCKESR, TPD, TFAW,
+ TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, FBIO_CFG6, ODT_WRITE, ODT_READ,
+ FBIO_CFG5, CFG_DIG_DLL, CFG_DIG_DLL_PERIOD, DLL_XFORM_DQS0,
+ DLL_XFORM_DQS1, DLL_XFORM_DQS2, DLL_XFORM_DQS3, DLL_XFORM_DQS4,
+ DLL_XFORM_DQS5, DLL_XFORM_DQS6, DLL_XFORM_DQS7, DLL_XFORM_DQS8,
+ DLL_XFORM_DQS9, DLL_XFORM_DQS10, DLL_XFORM_DQS11, DLL_XFORM_DQS12,
+ DLL_XFORM_DQS13, DLL_XFORM_DQS14, DLL_XFORM_DQS15, DLL_XFORM_QUSE0,
+ DLL_XFORM_QUSE1, DLL_XFORM_QUSE2, DLL_XFORM_QUSE3, DLL_XFORM_QUSE4,
+ DLL_XFORM_QUSE5, DLL_XFORM_QUSE6, DLL_XFORM_QUSE7, DLL_XFORM_ADDR0,
+ DLL_XFORM_ADDR1, DLL_XFORM_ADDR2, DLL_XFORM_ADDR3, DLL_XFORM_ADDR4,
+ DLL_XFORM_ADDR5, DLL_XFORM_QUSE8, DLL_XFORM_QUSE9, DLL_XFORM_QUSE10,
+ DLL_XFORM_QUSE11, DLL_XFORM_QUSE12, DLL_XFORM_QUSE13, DLL_XFORM_QUSE14,
+ DLL_XFORM_QUSE15, DLI_TRIM_TXDQS0, DLI_TRIM_TXDQS1, DLI_TRIM_TXDQS2,
+ DLI_TRIM_TXDQS3, DLI_TRIM_TXDQS4, DLI_TRIM_TXDQS5, DLI_TRIM_TXDQS6,
+ DLI_TRIM_TXDQS7, DLI_TRIM_TXDQS8, DLI_TRIM_TXDQS9, DLI_TRIM_TXDQS10,
+ DLI_TRIM_TXDQS11, DLI_TRIM_TXDQS12, DLI_TRIM_TXDQS13, DLI_TRIM_TXDQS14,
+ DLI_TRIM_TXDQS15, DLL_XFORM_DQ0, DLL_XFORM_DQ1, DLL_XFORM_DQ2,
+ DLL_XFORM_DQ3, DLL_XFORM_DQ4, DLL_XFORM_DQ5, DLL_XFORM_DQ6,
+ DLL_XFORM_DQ7, XM2CMDPADCTRL, XM2CMDPADCTRL4, XM2CMDPADCTRL5,
+ XM2DQSPADCTRL2, XM2DQPADCTRL2, XM2DQPADCTRL3, XM2CLKPADCTRL,
+ XM2CLKPADCTRL2, XM2COMPPADCTRL, XM2VTTGENPADCTRL, XM2VTTGENPADCTRL2,
+ XM2VTTGENPADCTRL3, XM2DQSPADCTRL3, XM2DQSPADCTRL4, XM2DQSPADCTRL5,
+ XM2DQSPADCTRL6, DSR_VTTGEN_DRV, TXDSRVTTGEN, FBIO_SPARE, ZCAL_INTERVAL,
+ ZCAL_WAIT_CNT, MRS_WAIT_CNT, MRS_WAIT_CNT2, AUTO_CAL_CONFIG2,
+ AUTO_CAL_CONFIG3, AUTO_CAL_CONFIG, CTT, CTT_DURATION, CFG_PIPE,
+ DYN_SELF_REF_CONTROL, QPOP, EMEM_ARB_CFG, EMEM_ARB_OUTSTANDING_REQ,
+ EMEM_ARB_TIMING_RCD, EMEM_ARB_TIMING_RP, EMEM_ARB_TIMING_RC,
+ EMEM_ARB_TIMING_RAS, EMEM_ARB_TIMING_FAW, EMEM_ARB_TIMING_RRD,
+ EMEM_ARB_TIMING_RAP2PRE, EMEM_ARB_TIMING_WAP2PRE, EMEM_ARB_TIMING_R2R,
+ EMEM_ARB_TIMING_W2W, EMEM_ARB_TIMING_R2W, EMEM_ARB_TIMING_W2R,
+ EMEM_ARB_DA_TURNS, EMEM_ARB_DA_COVERS, EMEM_ARB_MISC0,
+ EMEM_ARB_RING1_THROTTLE
+
+- nvidia, burst-up-down-regs : a word array of burst register values
+ The order and contents of the registers are:
+ MLL_MPCORER_PTSA_RATE, PTSA_GRANT_DECREMENT, LATENCY_ALLOWANCE_XUSB_0,
+ LATENCY_ALLOWANCE_XUSB_1, LATENCY_ALLOWANCE_TSEC_0,
+ LATENCY_ALLOWANCE_SDMMCA_0,LATENCY_ALLOWANCE_SDMMCAA_0,
+ LATENCY_ALLOWANCE_SDMMC_0, LATENCY_ALLOWANCE_SDMMCAB_0,
+ LATENCY_ALLOWANCE_PPCS_0, LATENCY_ALLOWANCE_PPCS_1,
+ LATENCY_ALLOWANCE_MPCORE_0, LATENCY_ALLOWANCE_MPCORELP_0,
+ LATENCY_ALLOWANCE_HC_0, LATENCY_ALLOWANCE_HC_1,
+ LATENCY_ALLOWANCE_AVPC_0, LATENCY_ALLOWANCE_GPU_0,
+ LATENCY_ALLOWANCE_MSENC_0, LATENCY_ALLOWANCE_HDA_0,
+ LATENCY_ALLOWANCE_VIC_0, LATENCY_ALLOWANCE_VI2_0,
+ LATENCY_ALLOWANCE_ISP2_0, LATENCY_ALLOWANCE_ISP2_1,
+ LATENCY_ALLOWANCE_ISP2B_0, LATENCY_ALLOWANCE_ISP2B_1,
+ LATENCY_ALLOWANCE_VDE_0, LATENCY_ALLOWANCE_VDE_1,
+ LATENCY_ALLOWANCE_VDE_2, LATENCY_ALLOWANCE_VDE_3,
+ LATENCY_ALLOWANCE_SATA_0, LATENCY_ALLOWANCE_AFI_0
+
+- nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change
+- nvidia,emc-acal-interval : EMC_AUTO_CAL_INTERVAL
+- nvidia,emc-ctt-term_ctrl : Configure CTT termination output drive strength
+- nvidia,emc-cfg : Configuration Register
+- nvidia,emc-cfg-2 : EMC Configuration 2
+- nvidia,emc-sel-dpd-ctrl : Configures functional SEL_DPD modes
+- nvidia,emc-cfg-dig-dll : Configure Digital DLL.
+- nvidia,emc-mode-0 : Mode Register 0
+- nvidia,emc-mode-1 : Mode Register 1
+- nvidia,emc-mode-2 : Mode Register 2
+- nvidia,emc-mode-4 : Mode Register 4
+
+optional properties:
+- nvidia,gk20a-min-mv : gpu min voltage
+
+ emc-table@40800 {
+ compatible = "nvidia,tegra12-emc-table";
+ nvidia,revision = <0>;
+ nvidia,dvfs-version = "04_40800_0_V5.0.1_V0.3";
+ clock-frequency = <40800>;
+ nvidia,emc-min-mv = <0>;
+ nvidia,gk20a-min-mv = <800>;
+ nvidia,source = "pllp_out0";
+ nvidia,src-sel-reg = <0>;
+ nvidia,burst-regs-num = <167>;
+ nvidia,burst-up-down-regs-num = <31>;
+ nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0>;
+ nvidia,emc-burst-up-down-regs = <
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0>;
+ nvidia,emc-zcal-cnt-long = <0>;
+ nvidia,emc-acal-interval = <0>;
+ nvidia,emc-ctt-term_ctrl = <0>;
+ nvidia,emc-cfg = <0>;
+ nvidia,emc-cfg-2 = <0>;
+ nvidia,emc-sel-dpd-ctrl = <0>;
+ nvidia,emc-cfg-dig-dll = <0>;
+ nvidia,emc-mode-0 = <0>;
+ nvidia,emc-mode-1 = <0>;
+ nvidia,emc-mode-2 = <0>;
+ nvidia,emc-mode-4 = <0>;
+ };
diff --git a/arch/arm/boot/dts/tegra124-tn8-emc.dtsi b/arch/arm/boot/dts/tegra124-tn8-emc.dtsi
new file mode 100644
index 000000000000..2f0837fdee2d
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-tn8-emc.dtsi
@@ -0,0 +1,2010 @@
+memory-controller@7001b000 {
+ emc-table@40800 {
+ compatible = "nvidia,tegra12-emc-table";
+ nvidia,revision = <0x15>;
+ nvidia,dvfs-version = "04_40800_0_V5.0.1_V0.3";
+ clock-frequency = <40800>;
+ nvidia,emc-min-mv = <800>;
+ nvidia,gk20a-min-mv = <800>;
+ nvidia,source = "pllp_out0";
+ nvidia,src-sel-reg = <0x40000006>;
+ nvidia,burst-regs-num = <167>;
+ nvidia,burst-up-down-regs-num = <31>;
+ nvidia,emc-registers = <
+ 0x00000001
+ 0x0000000a
+ 0x00000000
+ 0x00000001
+ 0x00000000
+ 0x00000004
+ 0x0000000a
+ 0x00000003
+ 0x0000000b
+ 0x00000000
+ 0x00000000
+ 0x00000003
+ 0x00000003
+ 0x00000000
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000002
+ 0x00000000
+ 0x00000005
+ 0x00000005
+ 0x00010000
+ 0x00000004
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000004
+ 0x0000000c
+ 0x0000000d
+ 0x0000000f
+ 0x0000012e
+ 0x00000000
+ 0x0000004b
+ 0x00000002
+ 0x00000002
+ 0x00000001
+ 0x00000000
+ 0x00000008
+ 0x0000000f
+ 0x0000000b
+ 0x0000000b
+ 0x00000004
+ 0x00000005
+ 0x00000004
+ 0x00000000
+ 0x00000000
+ 0x00000005
+ 0x00000005
+ 0x00000138
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x1069aa98
+ 0x002c00a0
+ 0x00008000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x0007c000
+ 0x0007c000
+ 0x0007c000
+ 0x0007c000
+ 0x00007c00
+ 0x00007c00
+ 0x00007c00
+ 0x00007c00
+ 0x100002a0
+ 0x00000000
+ 0x00111111
+ 0x0030a11c
+ 0x00000000
+ 0x00000000
+ 0x77ffc085
+ 0x00000e0e
+ 0x81f1f108
+ 0x07070004
+ 0x0000003f
+ 0x016eeeee
+ 0x51451400
+ 0x00514514
+ 0x00514514
+ 0x51451400
+ 0x0505003f
+ 0x00000014
+ 0x00000000
+ 0x00000000
+ 0x00000042
+ 0x000e000e
+ 0x000e000e
+ 0x00000000
+ 0x00000000
+ 0xa1430000
+ 0x00000000
+ 0x00000004
+ 0x0000f2f3
+ 0x80000364
+ 0x0000000a
+ 0xb0000001
+ 0x80000017
+ 0x00000001
+ 0x00000001
+ 0x00000002
+ 0x00000000
+ 0x00000002
+ 0x00000001
+ 0x00000002
+ 0x00000008
+ 0x00000003
+ 0x00000002
+ 0x00000003
+ 0x00000006
+ 0x06030203
+ 0x000a0402
+ 0x74c30303
+ 0x001f0000>;
+ nvidia,emc-burst-up-down-regs = <
+ 0x00000001
+ 0x00000014
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff0049
+ 0x00ff0080
+ 0x00ff0004
+ 0x00ff0004
+ 0x000800ff
+ 0x000000ff
+ 0x00ff0004
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff0024
+ 0x00ff00ff
+ 0x000000ff
+ 0x000000ff
+ 0x00ff00ff
+ 0x000000ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-acal-interval = <0x001fffff>;
+ nvidia,emc-ctt-term_ctrl = <0x00000802>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x00000885>;
+ nvidia,emc-sel-dpd-ctrl = <0x0004012c>;
+ nvidia,emc-cfg-dig-dll = <0x002c0068>;
+ nvidia,emc-mode-0 = <0x80001221>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ };
+ emc-table@68000 {
+ compatible = "nvidia,tegra12-emc-table";
+ nvidia,revision = <0x15>;
+ nvidia,dvfs-version = "04_68000_0_V5.0.1_V0.3";
+ clock-frequency = <68000>;
+ nvidia,emc-min-mv = <800>;
+ nvidia,gk20a-min-mv = <800>;
+ nvidia,source = "pllp_out0";
+ nvidia,src-sel-reg = <0x4000000a>;
+ nvidia,burst-regs-num = <167>;
+ nvidia,burst-up-down-regs-num = <31>;
+ nvidia,emc-registers = <
+ 0x00000003
+ 0x00000011
+ 0x00000000
+ 0x00000002
+ 0x00000000
+ 0x00000004
+ 0x0000000a
+ 0x00000003
+ 0x0000000b
+ 0x00000000
+ 0x00000000
+ 0x00000003
+ 0x00000003
+ 0x00000000
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000002
+ 0x00000000
+ 0x00000005
+ 0x00000005
+ 0x00010000
+ 0x00000004
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000004
+ 0x0000000c
+ 0x0000000d
+ 0x0000000f
+ 0x00000202
+ 0x00000000
+ 0x00000080
+ 0x00000002
+ 0x00000002
+ 0x00000001
+ 0x00000000
+ 0x0000000f
+ 0x0000000f
+ 0x00000013
+ 0x00000013
+ 0x00000004
+ 0x00000005
+ 0x00000004
+ 0x00000001
+ 0x00000000
+ 0x00000005
+ 0x00000005
+ 0x00000213
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x1069aa98
+ 0x002c00a0
+ 0x00008000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x0007c000
+ 0x0007c000
+ 0x0007c000
+ 0x0007c000
+ 0x00007c00
+ 0x00007c00
+ 0x00007c00
+ 0x00007c00
+ 0x100002a0
+ 0x00000000
+ 0x00111111
+ 0x0030a11c
+ 0x00000000
+ 0x00000000
+ 0x77ffc085
+ 0x00000e0e
+ 0x81f1f108
+ 0x07070004
+ 0x0000003f
+ 0x016eeeee
+ 0x51451400
+ 0x00514514
+ 0x00514514
+ 0x51451400
+ 0x0505003f
+ 0x00000022
+ 0x00000000
+ 0x00000000
+ 0x00000042
+ 0x000e000e
+ 0x000e000e
+ 0x00000000
+ 0x00000000
+ 0xa1430000
+ 0x00000000
+ 0x00000004
+ 0x0000f2f3
+ 0x8000050e
+ 0x0000000a
+ 0x00000001
+ 0x8000001e
+ 0x00000001
+ 0x00000001
+ 0x00000002
+ 0x00000000
+ 0x00000002
+ 0x00000001
+ 0x00000002
+ 0x00000008
+ 0x00000003
+ 0x00000002
+ 0x00000003
+ 0x00000006
+ 0x06030203
+ 0x000a0402
+ 0x74230403
+ 0x001f0000>;
+ nvidia,emc-burst-up-down-regs = <
+ 0x00000001
+ 0x00000021
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00b0
+ 0x00ff00ff
+ 0x00ff00ec
+ 0x00ff00ff
+ 0x00ff00ec
+ 0x00e90049
+ 0x00ff0080
+ 0x00ff0004
+ 0x00ff0004
+ 0x000800ff
+ 0x000000ff
+ 0x00ff0004
+ 0x00ff00ff
+ 0x00ff00a3
+ 0x00ff0024
+ 0x00ff00ff
+ 0x000000ff
+ 0x000000ef
+ 0x00ff00ff
+ 0x000000ef
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ee00ef
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-acal-interval = <0x001fffff>;
+ nvidia,emc-ctt-term_ctrl = <0x00000802>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x00000885>;
+ nvidia,emc-sel-dpd-ctrl = <0x0004012c>;
+ nvidia,emc-cfg-dig-dll = <0x002c0068>;
+ nvidia,emc-mode-0 = <0x80001221>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ };
+ emc-table@102000 {
+ compatible = "nvidia,tegra12-emc-table";
+ nvidia,revision = <0x15>;
+ nvidia,dvfs-version = "04_102000_0_V5.0.1_V0.3";
+ clock-frequency = <102000>;
+ nvidia,emc-min-mv = <800>;
+ nvidia,gk20a-min-mv = <800>;
+ nvidia,source = "pllp_out0";
+ nvidia,src-sel-reg = <0x40000006>;
+ nvidia,burst-regs-num = <167>;
+ nvidia,burst-up-down-regs-num = <31>;
+ nvidia,emc-registers = <
+ 0x00000004
+ 0x0000001a
+ 0x00000000
+ 0x00000003
+ 0x00000001
+ 0x00000004
+ 0x0000000a
+ 0x00000003
+ 0x0000000b
+ 0x00000001
+ 0x00000001
+ 0x00000003
+ 0x00000003
+ 0x00000000
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000002
+ 0x00000000
+ 0x00000005
+ 0x00000005
+ 0x00010000
+ 0x00000004
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000004
+ 0x0000000c
+ 0x0000000d
+ 0x0000000f
+ 0x00000304
+ 0x00000000
+ 0x000000c1
+ 0x00000002
+ 0x00000002
+ 0x00000001
+ 0x00000000
+ 0x00000018
+ 0x0000000f
+ 0x0000001c
+ 0x0000001c
+ 0x00000004
+ 0x00000005
+ 0x00000004
+ 0x00000003
+ 0x00000000
+ 0x00000005
+ 0x00000005
+ 0x0000031c
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x1069aa98
+ 0x002c00a0
+ 0x00008000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x0007c000
+ 0x0007c000
+ 0x0007c000
+ 0x0007c000
+ 0x00007c00
+ 0x00007c00
+ 0x00007c00
+ 0x00007c00
+ 0x100002a0
+ 0x00000000
+ 0x00111111
+ 0x0030a11c
+ 0x00000000
+ 0x00000000
+ 0x77ffc085
+ 0x00000e0e
+ 0x81f1f108
+ 0x07070004
+ 0x0000003f
+ 0x016eeeee
+ 0x51451400
+ 0x00514514
+ 0x00514514
+ 0x51451400
+ 0x0505003f
+ 0x00000033
+ 0x00000000
+ 0x00000000
+ 0x00000042
+ 0x000e000e
+ 0x000e000e
+ 0x00000000
+ 0x00000000
+ 0xa1430000
+ 0x00000000
+ 0x00000004
+ 0x0000f2f3
+ 0x80000713
+ 0x0000000a
+ 0x08000001
+ 0x80000026
+ 0x00000001
+ 0x00000001
+ 0x00000003
+ 0x00000000
+ 0x00000002
+ 0x00000001
+ 0x00000002
+ 0x00000008
+ 0x00000003
+ 0x00000002
+ 0x00000003
+ 0x00000006
+ 0x06030203
+ 0x000a0403
+ 0x73c30504
+ 0x001f0000>;
+ nvidia,emc-burst-up-down-regs = <
+ 0x00000001
+ 0x00000031
+ 0x00ff00da
+ 0x00ff00da
+ 0x00ff0075
+ 0x00ff00ff
+ 0x00ff009d
+ 0x00ff00ff
+ 0x00ff009d
+ 0x009b0049
+ 0x00ff0080
+ 0x00ff0004
+ 0x00ff0004
+ 0x000800ad
+ 0x000000ff
+ 0x00ff0004
+ 0x00ff00c6
+ 0x00ff006d
+ 0x00ff0024
+ 0x00ff00d6
+ 0x000000ff
+ 0x0000009f
+ 0x00ff00ff
+ 0x0000009f
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x009f00a0
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00da>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-acal-interval = <0x001fffff>;
+ nvidia,emc-ctt-term_ctrl = <0x00000802>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x00000885>;
+ nvidia,emc-sel-dpd-ctrl = <0x0004012c>;
+ nvidia,emc-cfg-dig-dll = <0x002c0068>;
+ nvidia,emc-mode-0 = <0x80001221>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ };
+ emc-table@204000 {
+ compatible = "nvidia,tegra12-emc-table";
+ nvidia,revision = <0x15>;
+ nvidia,dvfs-version = "04_204000_0_V5.0.1_V0.3";
+ clock-frequency = <204000>;
+ nvidia,emc-min-mv = <800>;
+ nvidia,gk20a-min-mv = <800>;
+ nvidia,source = "pllp_out0";
+ nvidia,src-sel-reg = <0x40000002>;
+ nvidia,burst-regs-num = <167>;
+ nvidia,burst-up-down-regs-num = <31>;
+ nvidia,emc-registers = <
+ 0x00000009
+ 0x00000035
+ 0x00000000
+ 0x00000006
+ 0x00000002
+ 0x00000005
+ 0x0000000a
+ 0x00000003
+ 0x0000000b
+ 0x00000002
+ 0x00000002
+ 0x00000003
+ 0x00000003
+ 0x00000000
+ 0x00000005
+ 0x00000005
+ 0x00000006
+ 0x00000002
+ 0x00000000
+ 0x00000004
+ 0x00000006
+ 0x00010000
+ 0x00000004
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000003
+ 0x0000000d
+ 0x0000000f
+ 0x00000011
+ 0x00000607
+ 0x00000000
+ 0x00000181
+ 0x00000002
+ 0x00000002
+ 0x00000001
+ 0x00000000
+ 0x00000032
+ 0x0000000f
+ 0x00000038
+ 0x00000038
+ 0x00000004
+ 0x00000005
+ 0x00000004
+ 0x00000007
+ 0x00000000
+ 0x00000005
+ 0x00000005
+ 0x00000638
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x1069aa98
+ 0x002c00a0
+ 0x00008000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00064000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00008000
+ 0x00000000
+ 0x00000000
+ 0x00008000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x0007c000
+ 0x0007c000
+ 0x0007c000
+ 0x0007c000
+ 0x00007c00
+ 0x00007c00
+ 0x00007c00
+ 0x00007c00
+ 0x100002a0
+ 0x00000000
+ 0x00111111
+ 0x0030a11c
+ 0x00000000
+ 0x00000000
+ 0x77ffc085
+ 0x00000707
+ 0x81f1f108
+ 0x07070004
+ 0x0000003f
+ 0x016eeeee
+ 0x51451400
+ 0x00514514
+ 0x00514514
+ 0x51451400
+ 0x0505003f
+ 0x00000000
+ 0x00000000
+ 0x00020000
+ 0x00000100
+ 0x000e000e
+ 0x000e000e
+ 0x00000000
+ 0x00000000
+ 0xa1430000
+ 0x00000000
+ 0x00000004
+ 0x0000d2b3
+ 0x80000d22
+ 0x0000000a
+ 0x01000003
+ 0x80000040
+ 0x00000001
+ 0x00000001
+ 0x00000004
+ 0x00000002
+ 0x00000004
+ 0x00000001
+ 0x00000002
+ 0x00000008
+ 0x00000003
+ 0x00000002
+ 0x00000004
+ 0x00000006
+ 0x06040203
+ 0x000a0404
+ 0x73840a05
+ 0x001f0000>;
+ nvidia,emc-burst-up-down-regs = <
+ 0x00000001
+ 0x00000062
+ 0x00ff006d
+ 0x00ff006d
+ 0x00ff003c
+ 0x00ff00af
+ 0x00ff004f
+ 0x00ff00af
+ 0x00ff004f
+ 0x004e0049
+ 0x00ff0080
+ 0x00ff0004
+ 0x00ff0004
+ 0x00080057
+ 0x000000ff
+ 0x00ff0004
+ 0x00ff0063
+ 0x00ff0036
+ 0x00ff0024
+ 0x00ff006b
+ 0x000000ff
+ 0x00000050
+ 0x00ff00ff
+ 0x00000050
+ 0x00ff00ff
+ 0x00d400ff
+ 0x00510050
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff00c6
+ 0x00ff006d>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-acal-interval = <0x001fffff>;
+ nvidia,emc-ctt-term_ctrl = <0x00000802>;
+ nvidia,emc-cfg = <0x73200000>;
+ nvidia,emc-cfg-2 = <0x0000088d>;
+ nvidia,emc-sel-dpd-ctrl = <0x0004012c>;
+ nvidia,emc-cfg-dig-dll = <0x002c0068>;
+ nvidia,emc-mode-0 = <0x80001221>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ };
+ emc-table@312000 {
+ compatible = "nvidia,tegra12-emc-table";
+ nvidia,revision = <0x15>;
+ nvidia,dvfs-version = "04_312000_2_V5.0.1_V0.3";
+ clock-frequency = <312000>;
+ nvidia,emc-min-mv = <820>;
+ nvidia,gk20a-min-mv = <800>;
+ nvidia,source = "pllm_out0";
+ nvidia,src-sel-reg = <0x00000002>;
+ nvidia,burst-regs-num = <167>;
+ nvidia,burst-up-down-regs-num = <31>;
+ nvidia,emc-registers = <
+ 0x0000000d
+ 0x00000050
+ 0x00000000
+ 0x00000009
+ 0x00000003
+ 0x00000004
+ 0x00000008
+ 0x00000002
+ 0x00000009
+ 0x00000003
+ 0x00000003
+ 0x00000002
+ 0x00000002
+ 0x00000000
+ 0x00000003
+ 0x00000003
+ 0x00000005
+ 0x00000002
+ 0x00000000
+ 0x00000002
+ 0x00000006
+ 0x00030000
+ 0x00000004
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000002
+ 0x0000000d
+ 0x0000000e
+ 0x00000010
+ 0x00000942
+ 0x00000000
+ 0x00000250
+ 0x00000001
+ 0x00000008
+ 0x00000001
+ 0x00000000
+ 0x0000004e
+ 0x0000000e
+ 0x00000055
+ 0x00000200
+ 0x00000004
+ 0x00000005
+ 0x00000004
+ 0x0000000a
+ 0x00000000
+ 0x00000005
+ 0x00000005
+ 0x00000982
+ 0x00000002
+ 0x00000000
+ 0x00000000
+ 0x1049b898
+ 0x002c00a0
+ 0x00008000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00040000
+ 0x00040000
+ 0x00000000
+ 0x00040000
+ 0x00040000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00040000
+ 0x00040000
+ 0x00040000
+ 0x00040000
+ 0x00004000
+ 0x00004000
+ 0x00004000
+ 0x00004000
+ 0x10000280
+ 0x00000000
+ 0x00111111
+ 0x01231339
+ 0x00000000
+ 0x00000000
+ 0x77ffc081
+ 0x00000505
+ 0x81f1f108
+ 0x07070004
+ 0x00000000
+ 0x016eeeee
+ 0x51451420
+ 0x00514514
+ 0x00514514
+ 0x51451400
+ 0x0000003f
+ 0x0000009c
+ 0x00000000
+ 0x00020000
+ 0x00000100
+ 0x0170000e
+ 0x0170000e
+ 0x00000000
+ 0x00000000
+ 0xa1430000
+ 0x00000000
+ 0x00000004
+ 0x0000d3b3
+ 0x8000138d
+ 0x00000009
+ 0x0b000004
+ 0x80000040
+ 0x00000001
+ 0x00000002
+ 0x00000007
+ 0x00000004
+ 0x00000005
+ 0x00000001
+ 0x00000002
+ 0x00000007
+ 0x00000002
+ 0x00000002
+ 0x00000004
+ 0x00000006
+ 0x06040202
+ 0x000b0607
+ 0x76e50f08
+ 0x001f0000>;
+ nvidia,emc-burst-up-down-regs = <
+ 0x00000005
+ 0x00000096
+ 0x00ff0047
+ 0x00ff0047
+ 0x00ff003c
+ 0x00ff0090
+ 0x00ff0041
+ 0x00ff0090
+ 0x00ff0041
+ 0x00330049
+ 0x00ff0080
+ 0x00ff0004
+ 0x00ff0004
+ 0x00080039
+ 0x000000ff
+ 0x00ff0004
+ 0x00ff0041
+ 0x00ff002c
+ 0x00ff0024
+ 0x00ff0046
+ 0x000000ff
+ 0x00000036
+ 0x00ff00ff
+ 0x00000036
+ 0x00ff00ff
+ 0x00d400ff
+ 0x00510034
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff0082
+ 0x00ff0047>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-acal-interval = <0x001fffff>;
+ nvidia,emc-ctt-term_ctrl = <0x00000802>;
+ nvidia,emc-cfg = <0x73340000>;
+ nvidia,emc-cfg-2 = <0x0000088d>;
+ nvidia,emc-sel-dpd-ctrl = <0x0004012c>;
+ nvidia,emc-cfg-dig-dll = <0x002c0068>;
+ nvidia,emc-mode-0 = <0x80000321>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ };
+ emc-table@396000 {
+ compatible = "nvidia,tegra12-emc-table";
+ nvidia,revision = <0x15>;
+ nvidia,dvfs-version = "04_396000_1_V5.0.1_V0.3";
+ clock-frequency = <396000>;
+ nvidia,emc-min-mv = <870>;
+ nvidia,gk20a-min-mv = <800>;
+ nvidia,source = "pllc_out0";
+ nvidia,src-sel-reg = <0x20000002>;
+ nvidia,burst-regs-num = <167>;
+ nvidia,burst-up-down-regs-num = <31>;
+ nvidia,emc-registers = <
+ 0x00000011
+ 0x00000066
+ 0x00000000
+ 0x0000000c
+ 0x00000004
+ 0x00000004
+ 0x00000008
+ 0x00000002
+ 0x0000000a
+ 0x00000004
+ 0x00000004
+ 0x00000002
+ 0x00000002
+ 0x00000000
+ 0x00000003
+ 0x00000003
+ 0x00000005
+ 0x00000002
+ 0x00000000
+ 0x00000002
+ 0x00000006
+ 0x00030000
+ 0x00000004
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000002
+ 0x0000000d
+ 0x0000000e
+ 0x00000010
+ 0x00000bd1
+ 0x00000000
+ 0x000002f4
+ 0x00000001
+ 0x00000008
+ 0x00000001
+ 0x00000000
+ 0x00000063
+ 0x0000000f
+ 0x0000006c
+ 0x00000200
+ 0x00000004
+ 0x00000005
+ 0x00000004
+ 0x0000000d
+ 0x00000000
+ 0x00000005
+ 0x00000005
+ 0x00000c11
+ 0x00000002
+ 0x00000000
+ 0x00000000
+ 0x1049b898
+ 0x002c00a0
+ 0x00008000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00030000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00070000
+ 0x00070000
+ 0x00000000
+ 0x00070000
+ 0x00070000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00044000
+ 0x00044000
+ 0x00044000
+ 0x00044000
+ 0x00004400
+ 0x00004400
+ 0x00004400
+ 0x00004400
+ 0x100002a0
+ 0x00000000
+ 0x00111111
+ 0x0123133d
+ 0x00000000
+ 0x00000000
+ 0x77ffc085
+ 0x00000505
+ 0x81f1f108
+ 0x07070004
+ 0x00000000
+ 0x016eeeee
+ 0x51451420
+ 0x00514514
+ 0x00514514
+ 0x51451400
+ 0x0000003f
+ 0x000000c6
+ 0x00000000
+ 0x00020000
+ 0x00000100
+ 0x015b000e
+ 0x015b000e
+ 0x00000000
+ 0x00000000
+ 0xa1430000
+ 0x00000000
+ 0x00000004
+ 0x0000d3b3
+ 0x8000188b
+ 0x00000009
+ 0x0f000005
+ 0x80000040
+ 0x00000001
+ 0x00000002
+ 0x00000009
+ 0x00000005
+ 0x00000007
+ 0x00000001
+ 0x00000002
+ 0x00000008
+ 0x00000002
+ 0x00000002
+ 0x00000004
+ 0x00000006
+ 0x06040202
+ 0x000d0709
+ 0x7586120a
+ 0x001f0000>;
+ nvidia,emc-burst-up-down-regs = <
+ 0x0000000a
+ 0x000000be
+ 0x00ff0038
+ 0x00ff0038
+ 0x00ff003c
+ 0x00ff0090
+ 0x00ff0041
+ 0x00ff0090
+ 0x00ff0041
+ 0x00280049
+ 0x00ff0080
+ 0x00ff0004
+ 0x00ff0004
+ 0x0008002d
+ 0x000000ff
+ 0x00ff0004
+ 0x00ff0033
+ 0x00ff0022
+ 0x00ff0024
+ 0x00ff0037
+ 0x000000ff
+ 0x00000036
+ 0x00ff00ff
+ 0x00000036
+ 0x00ff00ff
+ 0x00d400ff
+ 0x00510029
+ 0x00ff00ff
+ 0x00ff00ff
+ 0x00ff0066
+ 0x00ff0038>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-acal-interval = <0x001fffff>;
+ nvidia,emc-ctt-term_ctrl = <0x00000802>;
+ nvidia,emc-cfg = <0x73340000>;
+ nvidia,emc-cfg-2 = <0x0000088d>;
+ nvidia,emc-sel-dpd-ctrl = <0x0004012c>;
+ nvidia,emc-cfg-dig-dll = <0x002c0068>;
+ nvidia,emc-mode-0 = <0x80000521>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ };
+ emc-table@624000 {
+ compatible = "nvidia,tegra12-emc-table";
+ nvidia,revision = <0x15>;
+ nvidia,dvfs-version = "04_624000_2_NoRegCalcVersion_V0.3";
+ clock-frequency = <624000>;
+ nvidia,emc-min-mv = <910>;
+ nvidia,gk20a-min-mv = <900>;
+ nvidia,source = "pllm_ud";
+ nvidia,src-sel-reg = <0x80000000>;
+ nvidia,burst-regs-num = <167>;
+ nvidia,burst-up-down-regs-num = <31>;
+ nvidia,emc-registers = <
+ 0x0000001c
+ 0x000000a1
+ 0x00000000
+ 0x00000014
+ 0x00000007
+ 0x00000007
+ 0x0000000b
+ 0x00000003
+ 0x00000010
+ 0x00000007
+ 0x00000007
+ 0x00000002
+ 0x00000002
+ 0x00000000
+ 0x00000005
+ 0x00000005
+ 0x0000000a
+ 0x00000002
+ 0x00000000
+ 0x00000003
+ 0x0000000b
+ 0x00080000
+ 0x00000004
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000002
+ 0x00000012
+ 0x00000016
+ 0x00000018
+ 0x000012c3
+ 0x00000000
+ 0x000004b0
+ 0x00000002
+ 0x0000000d
+ 0x00000001
+ 0x00000000
+ 0x0000009c
+ 0x00000015
+ 0x000000a9
+ 0x00000200
+ 0x00000004
+ 0x00000005
+ 0x00000004
+ 0x00000016
+ 0x00000000
+ 0x00000007
+ 0x00000007
+ 0x00001304
+ 0x00000002
+ 0x00000000
+ 0x00000000
+ 0x1049b898
+ 0xe00d01b1
+ 0x00008000
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000008
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x0000400e
+ 0x0000400e
+ 0x00000000
+ 0x0000400e
+ 0x0000400e
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x100002a0
+ 0x00000000
+ 0x00111111
+ 0x0020013d
+ 0x00000000
+ 0x00000000
+ 0x77ffc085
+ 0x00000505
+ 0x81f1f108
+ 0x07070004
+ 0x00000000
+ 0x016eeeee
+ 0x51451420
+ 0x00514514
+ 0x00514514
+ 0x51451400
+ 0x0505003f
+ 0x00000000
+ 0x00000000
+ 0x00020000
+ 0x00000100
+ 0x0122000e
+ 0x0122000e
+ 0x00000000
+ 0x00000000
+ 0xa1430000
+ 0x00000000
+ 0x00000004
+ 0x000040a0
+ 0x80002617
+ 0x0000000e
+ 0x06000009
+ 0x80000040
+ 0x00000003
+ 0x00000004
+ 0x0000000f
+ 0x00000009
+ 0x0000000b
+ 0x00000001
+ 0x00000003
+ 0x0000000b
+ 0x00000002
+ 0x00000002
+ 0x00000005
+ 0x00000007
+ 0x07050202
+ 0x00130b0f
+ 0x736a1d10
+ 0x001f0000>;
+ nvidia,emc-burst-up-down-regs = <
+ 0x0000000f
+ 0x0000012b
+ 0x00a40038
+ 0x00a40038
+ 0x00a4003c
+ 0x00a40090
+ 0x00a40041
+ 0x00a40090
+ 0x00a40041
+ 0x00270049
+ 0x00a40080
+ 0x00a40004
+ 0x00a40004
+ 0x0008001c
+ 0x000000a4
+ 0x00a40004
+ 0x00a40020
+ 0x00a40018
+ 0x00a40024
+ 0x00a40023
+ 0x000000a4
+ 0x00000036
+ 0x00a400a4
+ 0x00000036
+ 0x00a400a4
+ 0x00d400ff
+ 0x00510029
+ 0x00a400a4
+ 0x00a400a4
+ 0x00a40065
+ 0x00a40024>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-acal-interval = <0x001fffff>;
+ nvidia,emc-ctt-term_ctrl = <0x00000802>;
+ nvidia,emc-cfg = <0x73300000>;
+ nvidia,emc-cfg-2 = <0x0000089d>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-cfg-dig-dll = <0xe00d0169>;
+ nvidia,emc-mode-0 = <0x80000b61>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200010>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ };
+ emc-table@792000 {
+ compatible = "nvidia,tegra12-emc-table";
+ nvidia,revision = <0x15>;
+ nvidia,dvfs-version = "04_792000_2_V5.0.1_V0.3";
+ clock-frequency = <792000>;
+ nvidia,emc-min-mv = <1000>;
+ nvidia,gk20a-min-mv = <1100>;
+ nvidia,source = "pllc_ud";
+ nvidia,src-sel-reg = <0xe0000000>;
+ nvidia,burst-regs-num = <167>;
+ nvidia,burst-up-down-regs-num = <31>;
+ nvidia,emc-registers = <
+ 0x00000024
+ 0x000000cc
+ 0x00000000
+ 0x00000019
+ 0x0000000a
+ 0x00000007
+ 0x0000000d
+ 0x00000004
+ 0x00000013
+ 0x0000000a
+ 0x0000000a
+ 0x00000003
+ 0x00000002
+ 0x00000000
+ 0x00000006
+ 0x00000006
+ 0x0000000b
+ 0x00000002
+ 0x00000000
+ 0x00000003
+ 0x0000000c
+ 0x00090000
+ 0x00000004
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000002
+ 0x00000013
+ 0x00000018
+ 0x0000001a
+ 0x000017e2
+ 0x00000000
+ 0x000005f8
+ 0x00000003
+ 0x00000011
+ 0x00000001
+ 0x00000000
+ 0x000000c6
+ 0x00000018
+ 0x000000d6
+ 0x00000200
+ 0x00000005
+ 0x00000006
+ 0x00000005
+ 0x0000001d
+ 0x00000000
+ 0x00000008
+ 0x00000008
+ 0x00001822
+ 0x00000002
+ 0x00000000
+ 0x00000000
+ 0x1049b898
+ 0xe00701b1
+ 0x00008000
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000006
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x0000400e
+ 0x0000400e
+ 0x00000000
+ 0x0000400e
+ 0x0000400e
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x0000000d
+ 0x0000000d
+ 0x0000000d
+ 0x0000000d
+ 0x0000000d
+ 0x0000000d
+ 0x0000000d
+ 0x0000000d
+ 0x100002a0
+ 0x00000000
+ 0x00111111
+ 0x0020013d
+ 0x00000000
+ 0x00000000
+ 0x77ffc085
+ 0x00000505
+ 0x81f1f108
+ 0x07070004
+ 0x00000000
+ 0x016eeeee
+ 0x61861820
+ 0x00514514
+ 0x00514514
+ 0x61861800
+ 0x0505003f
+ 0x00000000
+ 0x00000000
+ 0x00020000
+ 0x00000100
+ 0x00f8000e
+ 0x00f8000e
+ 0x00000000
+ 0x00000000
+ 0xa1430000
+ 0x00000000
+ 0x00000004
+ 0x000040a0
+ 0x80003012
+ 0x00000010
+ 0x0e00000b
+ 0x80000040
+ 0x00000004
+ 0x00000005
+ 0x00000013
+ 0x0000000c
+ 0x0000000f
+ 0x00000002
+ 0x00000003
+ 0x0000000c
+ 0x00000002
+ 0x00000002
+ 0x00000005
+ 0x00000008
+ 0x08050202
+ 0x00170e13
+ 0x734c2414
+ 0x001f0000>;
+ nvidia,emc-burst-up-down-regs = <
+ 0x00000013
+ 0x0000017c
+ 0x00810038
+ 0x00810038
+ 0x0081003c
+ 0x00810090
+ 0x00810041
+ 0x00810090
+ 0x00810041
+ 0x00270049
+ 0x00810080
+ 0x00810004
+ 0x00810004
+ 0x00080016
+ 0x00000081
+ 0x00810004
+ 0x00810019
+ 0x00810018
+ 0x00810024
+ 0x0081001c
+ 0x00000081
+ 0x00000036
+ 0x00810081
+ 0x00000036
+ 0x00810081
+ 0x00d400ff
+ 0x00510029
+ 0x00810081
+ 0x00810081
+ 0x00810065
+ 0x0081001c>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-acal-interval = <0x001fffff>;
+ nvidia,emc-ctt-term_ctrl = <0x00000802>;
+ nvidia,emc-cfg = <0x73300000>;
+ nvidia,emc-cfg-2 = <0x0000089d>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+ nvidia,emc-cfg-dig-dll = <0xe0070169>;
+ nvidia,emc-mode-0 = <0x80000d71>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200018>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ };
+ emc-table@924000 {
+ compatible = "nvidia,tegra12-emc-table";
+ nvidia,revision = <0x15>;
+ nvidia,dvfs-version = "04_924000_4_V5.0.1_V0.3";
+ clock-frequency = <924000>;
+ nvidia,emc-min-mv = <1100>;
+ nvidia,gk20a-min-mv = <1100>;
+ nvidia,source = "pllm_ud";
+ nvidia,src-sel-reg = <0x80000000>;
+ nvidia,burst-regs-num = <167>;
+ nvidia,burst-up-down-regs-num = <31>;
+ nvidia,emc-registers = <
+ 0x0000002b
+ 0x000000f0
+ 0x00000000
+ 0x0000001e
+ 0x0000000b
+ 0x00000008
+ 0x0000000f
+ 0x00000005
+ 0x00000016
+ 0x0000000b
+ 0x0000000b
+ 0x00000004
+ 0x00000002
+ 0x00000000
+ 0x00000007
+ 0x00000007
+ 0x0000000e
+ 0x00000002
+ 0x00000000
+ 0x00000003
+ 0x0000000e
+ 0x000b0000
+ 0x00000004
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000002
+ 0x00000015
+ 0x0000001a
+ 0x0000001c
+ 0x00001be7
+ 0x00000000
+ 0x000006f9
+ 0x00000004
+ 0x00000015
+ 0x00000001
+ 0x00000000
+ 0x000000e7
+ 0x0000001b
+ 0x00000132
+ 0x00000200
+ 0x00000006
+ 0x00000007
+ 0x00000006
+ 0x00000022
+ 0x00000000
+ 0x0000000a
+ 0x0000000a
+ 0x00001c28
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x1049b898
+ 0xe00401b1
+ 0x00008000
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000003
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00040000
+ 0x00040000
+ 0x00000000
+ 0x00040000
+ 0x00040000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x00000000
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x0000000a
+ 0x100002a0
+ 0x00000000
+ 0x00111111
+ 0x0120113d
+ 0x00000000
+ 0x00000000
+ 0x77ffc085
+ 0x00000505
+ 0x81f1f108
+ 0x07070004
+ 0x00000000
+ 0x016eeeee
+ 0x5d75d720
+ 0x00514514
+ 0x00514514
+ 0x5d75d700
+ 0x0606003f
+ 0x00000000
+ 0x00000000
+ 0x00020000
+ 0x00000128
+ 0x00cd000e
+ 0x00cd000e
+ 0x00000000
+ 0x00000000
+ 0xa1430000
+ 0x00000000
+ 0x00000004
+ 0x00004080
+ 0x800037ea
+ 0x00000011
+ 0x0e00000d
+ 0x80000040
+ 0x00000005
+ 0x00000006
+ 0x00000016
+ 0x0000000e
+ 0x00000011
+ 0x00000002
+ 0x00000004
+ 0x0000000e
+ 0x00000002
+ 0x00000002
+ 0x00000006
+ 0x00000009
+ 0x09060202
+ 0x001a1016
+ 0x738e2a17
+ 0x001f0000>;
+ nvidia,emc-burst-up-down-regs = <
+ 0x00000017
+ 0x000001bb
+ 0x006e0038
+ 0x006e0038
+ 0x006e003c
+ 0x006e0090
+ 0x006e0041
+ 0x006e0090
+ 0x006e0041
+ 0x00270049
+ 0x006e0080
+ 0x006e0004
+ 0x006e0004
+ 0x00080016
+ 0x0000006e
+ 0x006e0004
+ 0x006e0019
+ 0x006e0018
+ 0x006e0024
+ 0x006e001b
+ 0x0000006e
+ 0x00000036
+ 0x006e006e
+ 0x00000036
+ 0x006e006e
+ 0x00d400ff
+ 0x00510029
+ 0x006e006e
+ 0x006e006e
+ 0x006e0065
+ 0x006e001c>;
+ nvidia,emc-zcal-cnt-long = <0x0000004c>;
+ nvidia,emc-acal-interval = <0x001fffff>;
+ nvidia,emc-ctt-term_ctrl = <0x00000802>;
+ nvidia,emc-cfg = <0x73300000>;
+ nvidia,emc-cfg-2 = <0x0000089d>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+ nvidia,emc-cfg-dig-dll = <0xe0040169>;
+ nvidia,emc-mode-0 = <0x80000f15>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200020>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ };
+};
+
diff --git a/arch/arm/boot/dts/tegra124-tn8-generic.dtsi b/arch/arm/boot/dts/tegra124-tn8-generic.dtsi
index e81c1fc9d80a..05ad82855ff4 100644
--- a/arch/arm/boot/dts/tegra124-tn8-generic.dtsi
+++ b/arch/arm/boot/dts/tegra124-tn8-generic.dtsi
@@ -248,3 +248,6 @@ regulators {
};
};
};
+
+/include/ "tegra124-tn8-emc.dtsi"
+
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index bd0528e7ad0c..f4f8d9876778 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -130,6 +130,8 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra3_emc.o
obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra11_emc.o
obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra12_emc.o
obj-$(CONFIG_ARCH_TEGRA_14x_SOC) += tegra14_emc.o
+obj-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra_emc_dt_parse.o
+obj-$(CONFIG_ARCH_TEGRA_12x_SOC) += tegra_emc_dt_parse.o
obj-y += tegra_emc.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
diff --git a/arch/arm/mach-tegra/board-ardbeg-memory.c b/arch/arm/mach-tegra/board-ardbeg-memory.c
index c9f6e691db47..92c06d636ff1 100644
--- a/arch/arm/mach-tegra/board-ardbeg-memory.c
+++ b/arch/arm/mach-tegra/board-ardbeg-memory.c
@@ -5471,8 +5471,13 @@ int __init ardbeg_emc_init(void)
switch (bi.board_id) {
case BOARD_E1780:
case BOARD_E1782:
- pr_info("Loading Ardbeg EMC tables.\n");
- tegra_emc_device.dev.platform_data = &ardbeg_emc_pdata;
+ if (of_machine_is_compatible("nvidia,tn8")) {
+ pr_info("Loading TN8 EMC tables from DeviceTree.\n");
+ } else {
+ pr_info("Loading Ardbeg EMC tables.\n");
+ tegra_emc_device.dev.platform_data =
+ &ardbeg_emc_pdata;
+ }
break;
case BOARD_E1792:
pr_info("Loading Ardbeg EMC tables.\n");
diff --git a/arch/arm/mach-tegra/tegra11_emc.c b/arch/arm/mach-tegra/tegra11_emc.c
index a869bc9c6f00..c96c8d84342a 100644
--- a/arch/arm/mach-tegra/tegra11_emc.c
+++ b/arch/arm/mach-tegra/tegra11_emc.c
@@ -40,6 +40,7 @@
#include "iomap.h"
#include "tegra11_emc.h"
#include "fuse.h"
+#include "tegra_emc_dt_parse.h"
#ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
static bool emc_enable = true;
@@ -1154,255 +1155,6 @@ static int purge_emc_table(unsigned long max_rate)
#define purge_emc_table(max_rate) (0)
#endif
-#ifdef CONFIG_OF
-static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np)
-{
- struct device_node *iter;
- u32 reg;
-
- for_each_child_of_node(np, iter) {
- if (of_property_read_u32(np, "nvidia,ram-code", &reg))
- continue;
- if (reg == tegra_get_bct_strapping())
- return of_node_get(iter);
- }
-
- return NULL;
-}
-
-static struct tegra11_emc_pdata *tegra_emc_dt_parse_pdata(
- struct platform_device *pdev)
-{
- struct device_node *np = pdev->dev.of_node;
- struct device_node *tnp, *iter;
- struct tegra11_emc_pdata *pdata;
- int ret, i, num_tables;
- u32 tegra_bct_strapping;
-
- if (!np)
- return NULL;
-
- tegra_bct_strapping = tegra_get_bct_strapping();
- if (of_find_property(np, "nvidia,use-ram-code", NULL)) {
- tnp = tegra_emc_ramcode_devnode(np);
- if (!tnp)
- dev_warn(&pdev->dev,
- "can't find emc table for ram-code 0x%02x\n",
- tegra_bct_strapping);
- } else
- tnp = of_node_get(np);
-
- if (!tnp)
- return NULL;
-
- num_tables = 0;
- for_each_child_of_node(tnp, iter)
- if (of_device_is_compatible(iter, "nvidia,tegra11-emc-table"))
- num_tables++;
-
- if (!num_tables) {
- pdata = NULL;
- goto out;
- }
-
- pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
- pdata->tables = devm_kzalloc(&pdev->dev,
- sizeof(*pdata->tables) * num_tables,
- GFP_KERNEL);
-
- i = 0;
- for_each_child_of_node(tnp, iter) {
- u32 u;
- const char *source_name;
-
- ret = of_property_read_u32(iter, "nvidia,revision", &u);
- if (ret) {
- dev_err(&pdev->dev, "no revision in %s\n",
- iter->full_name);
- continue;
- }
- pdata->tables[i].rev = u;
-
- ret = of_property_read_u32(iter, "clock-frequency", &u);
- if (ret) {
- dev_err(&pdev->dev, "no clock-frequency in %s\n",
- iter->full_name);
- continue;
- }
- pdata->tables[i].rate = u;
-
- ret = of_property_read_u32(iter, "nvidia,emc-min-mv", &u);
- if (ret) {
- dev_err(&pdev->dev, "no emc-min-mv in %s\n",
- iter->full_name);
- continue;
- }
- pdata->tables[i].emc_min_mv = u;
-
- ret = of_property_read_string(iter,
- "nvidia,source", &source_name);
- if (ret) {
- dev_err(&pdev->dev, "no source name in %s\n",
- iter->full_name);
- continue;
- }
- pdata->tables[i].src_name = source_name;
-
- ret = of_property_read_u32(iter, "nvidia,src-sel-reg", &u);
- if (ret) {
- dev_err(&pdev->dev, "no src-sel-reg in %s\n",
- iter->full_name);
- continue;
- }
- pdata->tables[i].src_sel_reg = u;
-
- ret = of_property_read_u32(iter, "nvidia,burst-regs-num", &u);
- if (ret) {
- dev_err(&pdev->dev, "no burst-regs-num in %s\n",
- iter->full_name);
- continue;
- }
- pdata->tables[i].burst_regs_num = u;
-
- ret = of_property_read_u32(iter, "nvidia,emc-trimmers-num", &u);
- if (ret) {
- dev_err(&pdev->dev, "no emc-trimmers-num in %s\n",
- iter->full_name);
- continue;
- }
- pdata->tables[i].emc_trimmers_num = u;
-
- ret = of_property_read_u32(iter,
- "nvidia,burst-up-down-regs-num", &u);
- if (ret) {
- dev_err(&pdev->dev, "no burst-up-down-regs-num in %s\n",
- iter->full_name);
- continue;
- }
- pdata->tables[i].burst_up_down_regs_num = u;
-
- ret = of_property_read_u32_array(iter, "nvidia,emc-registers",
- pdata->tables[i].burst_regs,
- pdata->tables[i].burst_regs_num);
- if (ret) {
- dev_err(&pdev->dev,
- "malformed emc-registers property in %s\n",
- iter->full_name);
- continue;
- }
-
- ret = of_property_read_u32_array(iter, "nvidia,emc-trimmers-0",
- pdata->tables[i].emc_trimmers_0,
- pdata->tables[i].emc_trimmers_num);
- if (ret) {
- dev_err(&pdev->dev,
- "malformed emc-trimmers-0 property in %s\n",
- iter->full_name);
- continue;
- }
-
- ret = of_property_read_u32_array(iter, "nvidia,emc-trimmers-1",
- pdata->tables[i].emc_trimmers_1,
- pdata->tables[i].emc_trimmers_num);
- if (ret) {
- dev_err(&pdev->dev,
- "malformed emc-trimmers-1 property in %s\n",
- iter->full_name);
- continue;
- }
-
- ret = of_property_read_u32_array(iter,
- "nvidia,emc-burst-up-down-regs",
- pdata->tables[i].burst_up_down_regs,
- pdata->tables[i].burst_up_down_regs_num);
- if (ret) {
- dev_err(&pdev->dev,
- "malformed emc-burst-up-down-regs property in %s\n",
- iter->full_name);
- continue;
- }
-
- ret = of_property_read_u32(iter, "nvidia,emc-zcal-cnt-long",
- &pdata->tables[i].emc_zcal_cnt_long);
- if (ret) {
- dev_err(&pdev->dev,
- "malformed emc-zcal-cnt-long property in %s\n",
- iter->full_name);
- continue;
- }
-
- ret = of_property_read_u32(iter, "nvidia,emc-acal-interval",
- &pdata->tables[i].emc_acal_interval);
- if (ret) {
- dev_err(&pdev->dev,
- "malformed emc-acal-interval property in %s\n",
- iter->full_name);
- continue;
- }
-
- ret = of_property_read_u32(iter, "nvidia,emc-cfg",
- &pdata->tables[i].emc_cfg);
- if (ret) {
- dev_err(&pdev->dev,
- "malformed emc-cfg property in %s\n",
- iter->full_name);
- continue;
- }
-
- ret = of_property_read_u32(iter, "nvidia,emc-mode-reset",
- &pdata->tables[i].emc_mode_reset);
- if (ret) {
- dev_err(&pdev->dev,
- "malformed emc-mode-reset property in %s\n",
- iter->full_name);
- continue;
- }
-
- ret = of_property_read_u32(iter, "nvidia,emc-mode-1",
- &pdata->tables[i].emc_mode_1);
- if (ret) {
- dev_err(&pdev->dev,
- "malformed emc-mode-1 property in %s\n",
- iter->full_name);
- continue;
- }
-
- ret = of_property_read_u32(iter, "nvidia,emc-mode-2",
- &pdata->tables[i].emc_mode_2);
- if (ret) {
- dev_err(&pdev->dev,
- "malformed emc-mode-2 property in %s\n",
- iter->full_name);
- continue;
- }
-
- ret = of_property_read_u32(iter, "nvidia,emc-mode-4",
- &pdata->tables[i].emc_mode_4);
- if (ret) {
- dev_err(&pdev->dev,
- "malformed emc-mode-4 property in %s\n",
- iter->full_name);
- continue;
- }
-
- of_property_read_u32(iter, "nvidia,emc-clock-latency-change",
- &pdata->tables[i].clock_change_latency);
- i++;
- }
- pdata->num_tables = i;
-
-out:
- of_node_put(tnp);
- return pdata;
-}
-#else
-static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
- struct platform_device *pdev)
-{
- return NULL;
-}
-#endif
-
static int init_emc_table(const struct tegra11_emc_table *table, int table_size)
{
int i, mv;
@@ -1616,7 +1368,7 @@ static int tegra11_emc_probe(struct platform_device *pdev)
pdata = pdev->dev.platform_data;
if (!pdata)
- pdata = (struct tegra11_emc_pdata *)tegra_emc_dt_parse_pdata(pdev);
+ pdata = tegra_emc_dt_parse_pdata(pdev);
if (!pdata) {
dev_err(&pdev->dev, "missing platform data\n");
diff --git a/arch/arm/mach-tegra/tegra12_emc.c b/arch/arm/mach-tegra/tegra12_emc.c
index acfee87ed6f5..17000fc24c9f 100644
--- a/arch/arm/mach-tegra/tegra12_emc.c
+++ b/arch/arm/mach-tegra/tegra12_emc.c
@@ -22,6 +22,7 @@
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
@@ -40,6 +41,7 @@
#include "dvfs.h"
#include "iomap.h"
#include "tegra12_emc.h"
+#include "tegra_emc_dt_parse.h"
#ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
static bool emc_enable = true;
@@ -1367,6 +1369,9 @@ static int tegra12_emc_probe(struct platform_device *pdev)
struct tegra12_emc_pdata *pdata;
struct resource *res;
+ if (tegra_emc_table)
+ return -EINVAL;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "missing register base\n");
@@ -1374,6 +1379,11 @@ static int tegra12_emc_probe(struct platform_device *pdev)
}
pdata = pdev->dev.platform_data;
+
+ if (!pdata) {
+ pdata = tegra_emc_dt_parse_pdata(pdev);
+ }
+
if (!pdata) {
dev_err(&pdev->dev, "missing platform data\n");
return -ENODATA;
@@ -1382,10 +1392,16 @@ static int tegra12_emc_probe(struct platform_device *pdev)
return init_emc_table(pdata->tables, pdata->num_tables);
}
+static struct of_device_id tegra12_emc_of_match[] = {
+ { .compatible = "nvidia,tegra12-emc", },
+ { },
+};
+
static struct platform_driver tegra12_emc_driver = {
.driver = {
.name = "tegra-emc",
.owner = THIS_MODULE,
+ .of_match_table = tegra12_emc_of_match,
},
.probe = tegra12_emc_probe,
};
diff --git a/arch/arm/mach-tegra/tegra_emc_dt_parse.c b/arch/arm/mach-tegra/tegra_emc_dt_parse.c
new file mode 100644
index 000000000000..bcbc0f8b9774
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_emc_dt_parse.c
@@ -0,0 +1,365 @@
+/*
+ * arch/arm/mach-tegra/tegra_emc_dt_parse.c
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <linux/platform_data/tegra_emc.h>
+
+#include "fuse.h"
+
+#ifdef CONFIG_OF
+static struct device_node *tegra_emc_ramcode_devnode(
+ struct device_node *np)
+{
+ struct device_node *iter;
+ u32 reg;
+
+ for_each_child_of_node(np, iter) {
+ if (of_property_read_u32(np, "nvidia,ram-code", &reg))
+ continue;
+ if (reg == tegra_get_bct_strapping())
+ return of_node_get(iter);
+ }
+
+ return NULL;
+}
+
+void *tegra_emc_dt_parse_pdata(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *tnp, *iter;
+ int ret, i, num_tables;
+ u32 tegra_bct_strapping;
+#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
+ struct tegra12_emc_pdata *pdata = NULL;
+ const char *comp = "nvidia,tegra12-emc-table";
+#elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
+ struct tegra11_emc_pdata *pdata = NULL;
+ const char *comp = "nvidia,tegra11-emc-table";
+#endif
+
+ tegra_bct_strapping = tegra_get_bct_strapping();
+
+ if (!np) {
+ dev_err(&pdev->dev,
+ "Unable to find memory-controller node\n");
+ return NULL;
+ }
+
+ if (of_find_property(np, "nvidia,use-ram-code", NULL)) {
+ tnp = tegra_emc_ramcode_devnode(np);
+
+ if (!tnp) {
+ dev_warn(&pdev->dev,
+ "can't find emc table for ram-code 0x%02x\n",
+ tegra_bct_strapping);
+ return NULL;
+ }
+ } else
+ tnp = of_node_get(np);
+
+ num_tables = 0;
+ for_each_child_of_node(tnp, iter) {
+ if (of_device_is_compatible(iter, comp))
+ num_tables++;
+ }
+
+ if (!num_tables) {
+ pdata = NULL;
+ goto out;
+ }
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ pdata->tables = devm_kzalloc(&pdev->dev,
+ sizeof(*pdata->tables) * num_tables,
+ GFP_KERNEL);
+
+ if (!pdata->tables)
+ goto out;
+
+ i = 0;
+ for_each_child_of_node(tnp, iter) {
+ u32 u;
+ const char *source_name;
+ const char *dvfs_ver;
+
+ ret = of_property_read_u32(iter, "nvidia,revision", &u);
+ if (ret) {
+ dev_err(&pdev->dev, "no revision in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].rev = u;
+
+ ret = of_property_read_u32(iter, "clock-frequency", &u);
+ if (ret) {
+ dev_err(&pdev->dev, "no clock-frequency in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].rate = u;
+
+ ret = of_property_read_u32(iter, "nvidia,emc-min-mv", &u);
+ if (ret) {
+ dev_err(&pdev->dev, "no emc-min-mv in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_min_mv = u;
+
+ ret = of_property_read_string(iter,
+ "nvidia,source", &source_name);
+ if (ret) {
+ dev_err(&pdev->dev, "no source name in %s\n",
+ iter->full_name);
+ continue;
+ }
+#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
+ strncpy(pdata->tables[i].src_name, source_name, 16);
+#else
+ pdata->tables[i].src_name = source_name;
+#endif
+ ret = of_property_read_u32(iter, "nvidia,src-sel-reg", &u);
+ if (ret) {
+ dev_err(&pdev->dev, "no src-sel-reg in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].src_sel_reg = u;
+
+ ret = of_property_read_u32(iter, "nvidia,burst-regs-num", &u);
+ if (ret) {
+ dev_err(&pdev->dev, "no burst-regs-num in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].burst_regs_num = u;
+
+ ret = of_property_read_u32(iter,
+ "nvidia,burst-up-down-regs-num", &u);
+ if (ret) {
+ dev_err(&pdev->dev, "no burst-up-down-regs-num in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].burst_up_down_regs_num = u;
+
+ ret = of_property_read_u32_array(iter, "nvidia,emc-registers",
+ pdata->tables[i].burst_regs,
+ pdata->tables[i].burst_regs_num);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-registers property in %s\n",
+ iter->full_name);
+ continue;
+ }
+
+ ret = of_property_read_u32_array(iter,
+ "nvidia,emc-burst-up-down-regs",
+ pdata->tables[i].burst_up_down_regs,
+ pdata->tables[i].burst_up_down_regs_num);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-burst-up-down-regs "
+ "property in %s\n",
+ iter->full_name);
+ continue;
+ }
+
+ ret = of_property_read_u32(iter,
+ "nvidia,emc-zcal-cnt-long", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-zcal-cnt-long property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_zcal_cnt_long = u;
+
+ ret = of_property_read_u32(iter,
+ "nvidia,emc-acal-interval", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-acal-interval property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_acal_interval = u;
+
+ ret = of_property_read_u32(iter, "nvidia,emc-cfg", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-cfg property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_cfg = u;
+
+ ret = of_property_read_u32(iter, "nvidia,emc-mode-reset", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-mode-reset property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_mode_reset = u;
+
+ ret = of_property_read_u32(iter, "nvidia,emc-mode-1", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-mode-1 property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_mode_1 = u;
+
+ ret = of_property_read_u32(iter, "nvidia,emc-mode-2", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-mode-2 property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_mode_2 = u;
+
+ ret = of_property_read_u32(iter, "nvidia,emc-mode-4", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-mode-4 property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_mode_4 = u;
+#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
+
+ ret = of_property_read_string(iter,
+ "nvidia,dvfs-version", &dvfs_ver);
+ if (ret) {
+ dev_err(&pdev->dev, "no dvfs version in %s\n",
+ iter->full_name);
+ continue;
+ }
+ strncpy(pdata->tables[i].table_id, dvfs_ver,
+ TEGRA12_MAX_TABLE_ID_LEN);
+
+ ret = of_property_read_u32(iter, "nvidia,gk20a-min-mv", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed gk20a-min-mv property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].gk20a_min_mv = u;
+
+ ret = of_property_read_u32(iter,
+ "nvidia,emc-ctt-term_ctrl", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-ctt-term_ctrl property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_ctt_term_ctrl = u;
+
+ ret = of_property_read_u32(iter, "nvidia,emc-cfg-2", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-cfg-2 property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_cfg_2 = u;
+
+ ret = of_property_read_u32(iter, "nvidia,emc-sel-dpd-ctrl", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-sel-dpd-ctrl property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_sel_dpd_ctrl = u;
+
+ ret = of_property_read_u32(iter, "nvidia,emc-cfg-dig-dll", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-cfg-dig-dll property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_cfg_dig_dll = u;
+#endif
+
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+
+ ret = of_property_read_u32(iter, "nvidia,emc-trimmers-num", &u);
+ if (ret) {
+ dev_err(&pdev->dev, "no emc-trimmers-num in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].emc_trimmers_num = u;
+
+ ret = of_property_read_u32_array(iter, "nvidia,emc-trimmers-0",
+ pdata->tables[i].emc_trimmers_0,
+ pdata->tables[i].emc_trimmers_num);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-trimmers-0 property in %s\n",
+ iter->full_name);
+ continue;
+ }
+ ret = of_property_read_u32_array(iter, "nvidia,emc-trimmers-1",
+ pdata->tables[i].emc_trimmers_1,
+ pdata->tables[i].emc_trimmers_num);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-trimmers-1 property in %s\n",
+ iter->full_name);
+ continue;
+ }
+
+ ret = of_property_read_u32(iter,
+ "nvidia,emc-clock-latency-change", &u);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "malformed emc-clock-latency-change in %s\n",
+ iter->full_name);
+ continue;
+ }
+ pdata->tables[i].clock_change_latency = u;
+#endif
+ i++;
+ }
+ pdata->num_tables = i;
+
+out:
+ of_node_put(tnp);
+ return pdata;
+}
+#else
+void *tegra_emc_dt_parse_pdata(struct platform_device *pdev)
+{
+ return NULL;
+}
+#endif
diff --git a/arch/arm/mach-tegra/tegra_emc_dt_parse.h b/arch/arm/mach-tegra/tegra_emc_dt_parse.h
new file mode 100644
index 000000000000..039d17e90822
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_emc_dt_parse.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-tegra/tegra_emc_dt_parse.h
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#ifndef __TEGRA_EMC_DT_PARSE_H__
+#define __TEGRA_EMC_DT_PARSE_H__
+
+void *tegra_emc_dt_parse_pdata(struct platform_device *pdev);
+
+#endif /* __TEGRA_EMC_DT_PARSE_H__ */
+
generated by cgit v1.2.3 (git 2.0.4) at 2025-01-19 11:57:32 +0000