diff options
| -rw-r--r-- | arch/arm/Kconfig | 10 | ||||
| -rw-r--r-- | arch/arm/mach-imx/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 3 |
3 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index af00d12b4803..8041d312b8e2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1391,6 +1391,16 @@ config ARM_ERRATA_773022 loop buffer may deliver incorrect instructions. This workaround disables the loop buffer to avoid the erratum. +config ARM_ERRATA_814220 + bool "ARM errata: Cache maintenance by set/way operations can execute out of order" + depends on CPU_V7 + help + The v7 ARM states that all cache and branch predictor maintenance operations + that do not specify an address execute, relative to each other, in program order. + However, because of this erratum, an L2 set/way cache maintenance operation can + overtake an L1 set/way cache maintenance operation. This ERRATA only affected the + Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 117100a2e1da..b883e2a07c56 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -861,6 +861,7 @@ config SOC_IMX6UL select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI select SOC_IMX6 + select ARM_ERRATA_814220 help This enables support for Freescale i.MX6 UltraLite processor. @@ -871,6 +872,7 @@ config SOC_IMX7 select ARM_GIC select HAVE_SMP select HAVE_IMX_DDRC + select ARM_ERRATA_814220 config SOC_IMX7D bool "i.MX7 Dual support" diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 778bcf88ee79..c994f5c0afeb 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -162,6 +162,9 @@ loop2: skip: add r10, r10, #2 @ increment cache number cmp r3, r10 +#ifdef CONFIG_ARM_ERRATA_814220 + dsb +#endif bgt flush_levels finished: mov r10, #0 @ swith back to cache level 0 |