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-rw-r--r--arch/arm/configs/imx6_updater_defconfig1
-rw-r--r--arch/arm/mach-mx6/cpu_op-mx6.c16
-rw-r--r--arch/arm/mach-mx6/pm.c4
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx6dl.h38
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx6q.h36
5 files changed, 56 insertions, 39 deletions
diff --git a/arch/arm/configs/imx6_updater_defconfig b/arch/arm/configs/imx6_updater_defconfig
index 3de43e66353d..e562767d1133 100644
--- a/arch/arm/configs/imx6_updater_defconfig
+++ b/arch/arm/configs/imx6_updater_defconfig
@@ -729,6 +729,7 @@ CONFIG_MTD_CFI_UTIL=y
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_IMX6X_WEIMNOR=y
# CONFIG_MTD_PHYSMAP_COMPAT is not set
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_PLATRAM is not set
diff --git a/arch/arm/mach-mx6/cpu_op-mx6.c b/arch/arm/mach-mx6/cpu_op-mx6.c
index 541861832543..210fdd536c57 100644
--- a/arch/arm/mach-mx6/cpu_op-mx6.c
+++ b/arch/arm/mach-mx6/cpu_op-mx6.c
@@ -342,17 +342,25 @@ void mx6_cpu_op_init(void)
{
unsigned int reg;
void __iomem *base;
- if (cpu_is_mx6q()) {
+ if (!cpu_is_mx6sl()) {
/*read fuse bit to know the max cpu freq : offset 0x440
- * bit[17:16]:SPEED_GRADING[1:0]*/
+ * bit[17:16]:SPEED_GRADING[1:0],for mx6dq/dl*/
base = IO_ADDRESS(OCOTP_BASE_ADDR);
reg = __raw_readl(base + 0x440);
reg &= (0x3 << OCOTP_SPEED_BIT_OFFSET);
reg >>= OCOTP_SPEED_BIT_OFFSET;
/*choose the little value to run lower max cpufreq*/
arm_max_freq = (reg > arm_max_freq) ? arm_max_freq : reg;
- } else
- arm_max_freq = CPU_AT_1GHz;/*mx6dl/sl max freq is 1Ghz*/
+ } else {
+ /*
+ * There is no SPEED_GRADING fuse bit on mx6sl,then do:
+ * If arm_max_freq set by default on CPU_AT_1_2GHz which mean
+ * there is no 'arm_freq' setting in cmdline from bootloader,
+ * force arm_max_freq to 1G. Else use 'arm_freq' setting.
+ */
+ if (arm_max_freq == CPU_AT_1_2GHz)
+ arm_max_freq = CPU_AT_1GHz;/*mx6sl max freq is 1Ghz*/
+ }
printk(KERN_INFO "arm_max_freq=%s\n", (arm_max_freq == CPU_AT_1_2GHz) ?
"1.2GHz" : ((arm_max_freq == CPU_AT_1GHz) ? "1GHz" : "800MHz"));
get_cpu_op = mx6_get_cpu_op;
diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c
index 9f736e4dbce4..6e306c279d20 100644
--- a/arch/arm/mach-mx6/pm.c
+++ b/arch/arm/mach-mx6/pm.c
@@ -317,8 +317,8 @@ static int mx6_suspend_enter(suspend_state_t state)
* ARM_POWER_OFF mode.
*/
if (state == PM_SUSPEND_MEM &&
- ((mx6dl_revision() == IMX_CHIP_REVISION_1_0) || mx6q_revision()
- <= IMX_CHIP_REVISION_1_1)) {
+ ((mx6dl_revision() == IMX_CHIP_REVISION_1_0) ||
+ (cpu_is_mx6q() && mx6q_revision() <= IMX_CHIP_REVISION_1_1))) {
state = PM_SUSPEND_STANDBY;
}
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h
index e2740ffce210..cfda6e768e78 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -76,6 +76,10 @@
#define MX6DL_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define MX6DL_WEIM_NOR_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SPEED_MED | PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP)
+
#define MX6DL_ADU_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_DSE_40ohm | PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_HYS | PAD_CTL_SPEED_MED)
@@ -1471,7 +1475,7 @@
IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D16__WEIM_WEIM_D_16 \
- IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D16__ECSPI1_SCLK \
IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, MX6DL_ECSPI_PAD_CTRL)
#define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN5 \
@@ -1490,7 +1494,7 @@
IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D17__WEIM_WEIM_D_17 \
- IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D17__ECSPI1_MISO \
IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, MX6DL_ECSPI_PAD_CTRL)
#define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN6 \
@@ -1509,7 +1513,7 @@
IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D18__WEIM_WEIM_D_18 \
- IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D18__ECSPI1_MOSI \
IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, MX6DL_ECSPI_PAD_CTRL)
#define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN7 \
@@ -1528,7 +1532,7 @@
IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D19__WEIM_WEIM_D_19 \
- IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D19__ECSPI1_SS1 \
IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, MX6DL_ECSPI_PAD_CTRL)
#define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN8 \
@@ -1549,7 +1553,7 @@
IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D20__WEIM_WEIM_D_20 \
- IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D20__ECSPI4_SS0 \
IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16 \
@@ -1568,7 +1572,7 @@
IOMUX_PAD(0x0524, 0x0154, 7, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D21__WEIM_WEIM_D_21 \
- IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D21__ECSPI4_SCLK \
IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17 \
@@ -1585,7 +1589,7 @@
IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D22__WEIM_WEIM_D_22 \
- IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D22__ECSPI4_MISO \
IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN1 \
@@ -1604,7 +1608,7 @@
IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D23__WEIM_WEIM_D_23 \
- IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS \
IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D23__UART3_CTS \
@@ -1625,7 +1629,7 @@
IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D24__WEIM_WEIM_D_24 \
- IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D24__ECSPI4_SS2 \
IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D24__UART3_TXD \
@@ -1646,7 +1650,7 @@
IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D25__WEIM_WEIM_D_25 \
- IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D25__ECSPI4_SS3 \
IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D25__UART3_TXD \
@@ -1667,7 +1671,7 @@
IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D26__WEIM_WEIM_D_26 \
- IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11 \
IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D26__IPU1_CSI0_D_1 \
@@ -1688,7 +1692,7 @@
IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D27__WEIM_WEIM_D_27 \
- IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13 \
IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D27__IPU1_CSI0_D_0 \
@@ -1709,7 +1713,7 @@
IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D28__WEIM_WEIM_D_28 \
- IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D28__I2C1_SDA \
IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, MX6DL_I2C_PAD_CTRL)
#define MX6DL_PAD_EIM_D28__ECSPI4_MOSI \
@@ -1730,7 +1734,7 @@
IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D29__WEIM_WEIM_D_29 \
- IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15 \
IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D29__ECSPI4_SS0 \
@@ -1749,7 +1753,7 @@
IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D30__WEIM_WEIM_D_30 \
- IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11 \
@@ -1770,7 +1774,7 @@
IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D31__WEIM_WEIM_D_31 \
- IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, MX6DL_WEIM_NOR_PAD_CTRL)
#define MX6DL_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12 \
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
index c1acc2417c16..db7e6616c4a2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
@@ -93,6 +93,10 @@
PAD_CTL_DSE_40ohm | PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+#define MX6Q_WEIM_NOR_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SPEED_MED | PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP)
+
#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
@@ -3902,7 +3906,7 @@
(_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
- (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
(_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
@@ -3917,7 +3921,7 @@
(_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
- (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D17__ECSPI1_MISO \
(_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
@@ -3934,7 +3938,7 @@
(_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
- (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
(_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
@@ -3951,7 +3955,7 @@
(_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
- (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
(_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
@@ -3968,7 +3972,7 @@
(_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
- (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
(_MX6Q_PAD_EIM_D20__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
@@ -3985,7 +3989,7 @@
(_MX6Q_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
- (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
(_MX6Q_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
@@ -4002,7 +4006,7 @@
(_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
- (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D22__ECSPI4_MISO \
(_MX6Q_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
@@ -4019,7 +4023,7 @@
(_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
- (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
(_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D23__UART3_CTS \
@@ -4055,7 +4059,7 @@
(_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
- (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
(_MX6Q_PAD_EIM_D24__ECSPI4_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D24__UART3_TXD \
@@ -4074,7 +4078,7 @@
(_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
- (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
(_MX6Q_PAD_EIM_D25__ECSPI4_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D25__UART3_TXD \
@@ -4093,7 +4097,7 @@
(_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
- (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
(_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
@@ -4112,7 +4116,7 @@
(_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
- (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
(_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
@@ -4131,7 +4135,7 @@
(_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
- (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D28__I2C1_SDA \
(_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
@@ -4150,7 +4154,7 @@
(_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
- (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
(_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
@@ -4167,7 +4171,7 @@
(_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
- (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
(_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
@@ -4184,7 +4188,7 @@
(_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
- (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(MX6Q_WEIM_NOR_PAD_CTRL))
#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
(_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 21:19:50 +0000