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-rw-r--r--arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
index 36dd76c92086..21bd7b8b18fe 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
@@ -1367,8 +1367,7 @@ NvRmPrivAp15PllDPowerControl(
// On exit from display clock configuration turn off PLLD power
// if it is disabled
if ((*pMipiPllVddOn) &&
- (NvRmPrivGetClockSourceFreq(NvRmClockSource_PllD0) <=
- NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM)))
+ (NvRmPrivGetClockSourceFreq(NvRmClockSource_PllD0) == 0))
{
NvRmPrivPmuRailControl(hRmDevice, NV_VDD_PLLD_ODM_ID, NV_FALSE);
*pMipiPllVddOn = NV_FALSE;