diff options
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts | 47 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi | 68 |
2 files changed, 115 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts index b1ffb7ad1f64..5c78ffb292bb 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts @@ -38,6 +38,25 @@ #address-cells = <1>; #size-cells = <0>; + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + reg_fec2_supply: fec2_nvcc { compatible = "regulator-fixed"; regulator-name = "fec2_nvcc"; @@ -330,6 +349,20 @@ >; }; + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + pinctrl_flexspi0: flexspi0grp { fsl,pins = < SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c @@ -607,6 +640,20 @@ status = "disabled"; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + &flexspi0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi0>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi index 04303a5958d0..28095417c7fb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi @@ -34,6 +34,25 @@ enable-active-high; }; + reg_can_en: regulator-can-gen { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + reg_audio: fixedregulator@0 { compatible = "regulator-fixed"; reg = <2>; @@ -233,6 +252,27 @@ >; }; + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 + SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 + >; + }; + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { fsl,pins = < SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 @@ -478,6 +518,27 @@ status = "disabled"; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + &mipi_csi_0 { #address-cells = <1>; #size-cells = <0>; @@ -609,6 +670,13 @@ gpio-controller; #gpio-cells = <2>; }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; }; &pd_dma_lpuart0 { |