diff options
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts | 50 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi | 18 |
2 files changed, 65 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts index ddde264722d4..44ec42ac3bed 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts @@ -25,6 +25,14 @@ stdout-patch = &uart2; }; + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -86,10 +94,29 @@ >; }; - pinctrl_uart2: uart1grp { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 >; }; @@ -383,12 +410,29 @@ }; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + resets = <&modem_reset>; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi index b5b381bc0cec..ecd9863c0a39 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi @@ -35,6 +35,7 @@ serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; + serial3 = &uart4; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; @@ -367,6 +368,8 @@ clocks = <&clk IMX8MM_CLK_UART1_ROOT>, <&clk IMX8MM_CLK_UART1_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -379,6 +382,8 @@ clocks = <&clk IMX8MM_CLK_UART3_ROOT>, <&clk IMX8MM_CLK_UART3_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -434,6 +439,19 @@ status = "disabled"; }; + uart4: serial@30a60000 { + compatible = "fsl,imx8mq-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x0 0x30a60000 0x0 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_UART4_ROOT>, + <&clk IMX8MM_CLK_UART4_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x0 0x32e40000 0x0 0x200>; |