diff options
| -rw-r--r-- | Documentation/devicetree/bindings/phy/mxs-usb-phy.txt | 1 | ||||
| -rw-r--r-- | drivers/usb/phy/phy-mxs-usb.c | 75 |
2 files changed, 74 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt index 6541a1e1e5f5..415dc0d05805 100644 --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt @@ -8,6 +8,7 @@ Required properties: * "fsl,vf610-usbphy" for Vybrid vf610 * "fsl,imx6sx-usbphy" for imx6sx * "fsl,imx6ul-usbphy" for imx6ul + * "fsl,imx7ulp-usbphy" for imx7ulp "fsl,imx23-usbphy" is still a fallback for other strings - reg: Should contain registers location and length - interrupts: Should contain phy interrupt diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c index 5407423b507c..4b7f4bb95eb3 100644 --- a/drivers/usb/phy/phy-mxs-usb.c +++ b/drivers/usb/phy/phy-mxs-usb.c @@ -27,6 +27,7 @@ #define DRIVER_NAME "mxs_phy" +/* Register Macro */ #define HW_USBPHY_PWD 0x00 #define HW_USBPHY_TX 0x10 #define HW_USBPHY_CTRL 0x30 @@ -44,6 +45,11 @@ #define GM_USBPHY_TX_TXCAL45DN(x) (((x) & 0xf) << 8) #define GM_USBPHY_TX_D_CAL(x) (((x) & 0xf) << 0) +/* imx7ulp */ +#define HW_USBPHY_PLL_SIC 0xa4 +#define HW_USBPHY_PLL_SIC_SET 0xa4 +#define HW_USBPHY_PLL_SIC_CLR 0xa8 + #define BM_USBPHY_CTRL_SFTRST BIT(31) #define BM_USBPHY_CTRL_CLKGATE BIT(30) #define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27) @@ -62,6 +68,12 @@ #define BM_USBPHY_IP_FIX (BIT(17) | BIT(18)) #define BM_USBPHY_DEBUG_CLKGATE BIT(30) +/* imx7ulp */ +#define BM_USBPHY_PLL_LOCK BIT(31) +#define BM_USBPHY_PLL_REG_ENABLE BIT(21) +#define BM_USBPHY_PLL_BYPASS BIT(16) +#define BM_USBPHY_PLL_POWER BIT(12) +#define BM_USBPHY_PLL_EN_USB_CLKS BIT(6) /* Anatop Registers */ #define ANADIG_REG_1P1_SET 0x114 @@ -179,7 +191,11 @@ static const struct mxs_phy_data imx6ul_phy_data = { MXS_PHY_HARDWARE_CONTROL_PHY2_CLK, }; +static const struct mxs_phy_data imx7ulp_phy_data = { +}; + static const struct of_device_id mxs_phy_dt_ids[] = { + { .compatible = "fsl,imx7ulp-usbphy", .data = &imx7ulp_phy_data, }, { .compatible = "fsl,imx6ul-usbphy", .data = &imx6sx_phy_data, }, { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, }, { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, }, @@ -218,6 +234,11 @@ static inline bool is_imx6ul_phy(struct mxs_phy *mxs_phy) return mxs_phy->data == &imx6ul_phy_data; } +static inline bool is_imx7ulp_phy(struct mxs_phy *mxs_phy) +{ + return mxs_phy->data == &imx7ulp_phy_data; +} + /* * PHY needs some 32K cycles to switch from 32K clock to * bus (such as AHB/AXI, etc) clock. @@ -241,14 +262,59 @@ static void mxs_phy_tx_init(struct mxs_phy *mxs_phy) } } +static int wait_for_pll_lock(const void __iomem *base) +{ + int loop_count = 100; + + /* Wait for PLL to lock */ + do { + if (readl(base + HW_USBPHY_PLL_SIC) & BM_USBPHY_PLL_LOCK) + break; + usleep_range(100, 150); + } while (loop_count-- > 0); + + return readl(base + HW_USBPHY_PLL_SIC) & BM_USBPHY_PLL_LOCK + ? 0 : -ETIMEDOUT; +} + +static int mxs_phy_pll_enable(void __iomem *base, bool enable) +{ + int ret = 0; + + if (enable) { + writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_SET); + writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_CLR); + writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_SET); + ret = wait_for_pll_lock(base); + if (ret) + return ret; + writel(BM_USBPHY_PLL_EN_USB_CLKS, base + + HW_USBPHY_PLL_SIC_SET); + } else { + writel(BM_USBPHY_PLL_EN_USB_CLKS, base + + HW_USBPHY_PLL_SIC_CLR); + writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_CLR); + writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_SET); + writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_CLR); + } + + return ret; +} + static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) { int ret; void __iomem *base = mxs_phy->phy.io_priv; + if (is_imx7ulp_phy(mxs_phy)) { + ret = mxs_phy_pll_enable(base, true); + if (ret) + return ret; + } + ret = stmp_reset_block(base + HW_USBPHY_CTRL); if (ret) - return ret; + goto disable_pll; if (mxs_phy->phy_3p0) { ret = regulator_enable(mxs_phy->phy_3p0); @@ -256,7 +322,7 @@ static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) dev_err(mxs_phy->phy.dev, "Failed to enable 3p0 regulator, ret=%d\n", ret); - return ret; + goto disable_pll; } } @@ -283,6 +349,11 @@ static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) mxs_phy_tx_init(mxs_phy); return 0; + +disable_pll: + if (is_imx7ulp_phy(mxs_phy)) + mxs_phy_pll_enable(base, false); + return ret; } /* Return true if the vbus is there */ |