diff options
-rw-r--r-- | Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 3 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts | 35 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi | 61 |
3 files changed, 97 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 6a3db76e4db7..32e17df380f6 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: -- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie", "fsl,imx8qm-pcie" +- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie", + "fsl,imx8qm-pcie","fsl,imx8mq-pcie" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts index 048c9c36fdce..2e0d33ed27ac 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts @@ -93,6 +93,23 @@ >; }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16 + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16 + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 @@ -175,6 +192,24 @@ status = "disabled"; }; +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &uart1 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi index 02a64799ca99..cf7dd7295ca7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi @@ -268,7 +268,7 @@ }; gpc: gpc@303a0000 { - compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc"; + compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon"; reg = <0x0 0x303a0000 0x0 0x10000>; interrupt-controller; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; @@ -669,4 +669,63 @@ clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; status = "disabled"; }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + pcie0: pcie@0x33800000 { + compatible = "fsl,imx8mq-pcie", "snps,dw-pcie"; + reg = <0x0 0x33800000 0x0 0x400000>, <0x0 0x1ff00000 0x0 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX_CG>, + <&clk IMX8MQ_CLK_PCIE1_PHY_CG>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; + ctrl-id = <0>; + status = "disabled"; + }; + + pcie1: pcie@0x33c00000 { + compatible = "fsl,imx8mq-pcie", "snps,dw-pcie"; + reg = <0x0 0x33c00000 0x0 0x400000>, <0x0 0x27f00000 0x0 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x20000000 0x0 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX_CG>, + <&clk IMX8MQ_CLK_PCIE2_PHY_CG>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; + ctrl-id = <1>; + status = "disabled"; + }; }; |