diff options
| -rw-r--r-- | arch/arm/boot/dts/imx6ull-colibri-aster.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6ull-colibri.dtsi | 6 |
3 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi index 589accd233ba..ba69ef18e8a8 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi @@ -296,10 +296,11 @@ /* #define SD_1_8 */ &usdhc1 { #ifdef SD_1_8 - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_cd_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_cd_usdhc1>; pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_cd_usdhc1>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_cd_usdhc1_sleep>; vqmmc-supply = <®_sd1_vmmc>; #else pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index 5605312f1a69..60db4afde849 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -338,10 +338,11 @@ /* #define SD_1_8 */ &usdhc1 { #ifdef SD_1_8 - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_cd_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_cd_usdhc1>; pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_cd_usdhc1>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_cd_usdhc1_sleep>; vqmmc-supply = <®_sd1_vmmc>; #else pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index b78eca1d9993..9abe212e2dec 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -599,6 +599,12 @@ >; }; + pinctrl_snvs_cd_usdhc1_sleep: snvs-usdhc1-cd-grp-slp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 + >; + }; + pinctrl_wifi_pdn: wifi-pdn { fsl,pins = < MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 |