diff options
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts | 72 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi | 75 |
2 files changed, 76 insertions, 71 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts index c8397bb6d456..24a370642674 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts @@ -4,74 +4,4 @@ */ #include "imx8qxp-mek-rpmsg.dts" - -/ { - panel { - compatible = "sii,43wvf1g"; - backlight = <&lcdif_backlight>; - status = "okay"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - display@disp1 { - compatible = "fsl,imx-lcdif-mux-display"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, - <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; - clock-names = "bypass_div", "pixel"; - assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; - assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; - fsl,lcdif-mux-regs = <&lcdif_mux_regs>; - fsl,interface-pix-fmt = "rgb666"; - power-domains = <&pd IMX_SC_R_LCD_0>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&dpu_disp1_lcdif>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; -}; - -&dpu_disp1_lcdif { - remote-endpoint = <&lcd_display_in>; -}; - -&iomuxc { - pinctrl_hog: hoggrp { - fsl,pins = < - IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x40000000 - >; - }; -}; - -&sai1 { - status = "disabled"; -}; - -&esai0 { - status = "disabled"; -}; - -&lpuart1 { - status = "disabled"; -}; +#include "imx8x-mek-dpu-lcdif.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi new file mode 100644 index 000000000000..172c0d2734be --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-mek-dpu-lcdif.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + panel { + compatible = "sii,43wvf1g"; + backlight = <&lcdif_backlight>; + status = "okay"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + display@disp1 { + compatible = "fsl,imx-lcdif-mux-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "bypass_div", "pixel"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + fsl,lcdif-mux-regs = <&lcdif_mux_regs>; + fsl,interface-pix-fmt = "rgb666"; + power-domains = <&pd IMX_SC_R_LCD_0>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&dpu_disp1_lcdif>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; +}; + +&dpu_disp1_lcdif { + remote-endpoint = <&lcd_display_in>; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x40000000 + >; + }; +}; + +&sai1 { + status = "disabled"; +}; + +&esai0 { + status = "disabled"; +}; + +&lpuart1 { + status = "disabled"; +}; |