diff options
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 22 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi | 50 |
2 files changed, 70 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 45f12bf67c70..6b10944aa57c 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -377,6 +377,21 @@ status = "okay"; }; +&usbphy2 { + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -385,7 +400,12 @@ fsl,pins = < IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 0x00000021 - IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021 + >; + }; + + pinctrl_usbotg2: otg2 { + fsl,pins = < + IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi index 9e3256d65b7d..d1ca25c835e2 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -35,7 +35,7 @@ /* * usbotg1 and usbotg2 share one clcok * scfw disable clock access and keep it always on - * incase other core (M4) use one of these. + * in case other core (M4) use one of these. */ clocks = <&clk_dummy>; }; @@ -45,6 +45,18 @@ }; &conn_subsys { + + usb2_2_lpcg: clock-controller@5b280000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b280000 0x10000>; + #clock-cells = <1>; + + bit-offset = <28>; + clocks = <&conn_ipg_clk>; + clock-output-names = "usboh3_2_ahb_clk"; + power-domains = <&pd IMX_SC_R_USB_1_PHY>; + }; + conn_enet0_root_clk: clock-conn-enet0-root { compatible = "fixed-clock"; #clock-cells = <0>; @@ -89,4 +101,40 @@ clk_csr = <0>; status = "disabled"; }; + + usbphy2: usbphy@0x5b110000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x5b110000 0x1000>; + clocks = <&usb2_2_lpcg 0>; + power-domains = <&pd IMX_SC_R_USB_1_PHY>; + status = "disabled"; + }; + + usbotg2: usb@5b0e0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; + reg = <0x5b0e0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc2 0>; + /* + * usbotg1 and usbotg2 share one clcok + * scfw disable clock access and keep it always on + * in case other core (M4) use one of these. + */ + clocks = <&clk_dummy>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd IMX_SC_R_USB_1>; + status = "disabled"; + }; + + usbmisc2: usbmisc@5b0e0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x5b0e0200 0x200>; + }; + }; |