diff options
| -rw-r--r-- | arch/arm64/boot/dts/freescale/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts | 7 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dx-mek.dts | 35 |
3 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 10a6fb67dd4e..75c59c18b31e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640 imx8qxp-mek-jdi-wuxga-lvds0-panel.dtb \ imx8qxp-mek-jdi-wuxga-lvds1-panel.dtb \ imx8qxp-mek-dsi-rm67191.dtb \ + imx8dx-mek.dtb imx8dx-mek-rpmsg.dtb \ imx8qxp-lpddr4-val-a0.dtb \ imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \ imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \ diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts new file mode 100644 index 000000000000..a219f16323bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek-rpmsg.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8dx-mek.dts" +#include "imx8x-mek-rpmsg.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8dx-mek.dts b/arch/arm64/boot/dts/freescale/imx8dx-mek.dts new file mode 100644 index 000000000000..d0a59164d9f5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-mek.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; +#include "imx8dx.dtsi" +#include "imx8x-mek.dtsi" + +/ { + model = "Freescale i.MX8DX MEK"; + compatible = "fsl,imx8dx-mek", "fsl,imx8dx", "fsl,imx8qxp"; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; + alloc-ranges = <0 0x96000000 0 0x14000000>; + linux,cma-default; + }; + }; +}; + +&thermal_zones { + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +};
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