diff options
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 22 | ||||
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 |
2 files changed, 22 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi index b9b364b0ecc8..4de4481eee18 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -5,6 +5,23 @@ */ &dma_subsys { + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + reg = <0x5a0a0000 0x1000>; + interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&uart4_lpcg 1>, <&uart4_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_4>; + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma2 21 0 0>, + <&edma2 20 0 1>; + status = "disabled"; + }; + uart4_lpcg: clock-controller@5a4a0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a4a0000 0x10000>; @@ -135,17 +152,20 @@ &lpuart1 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; - power-domains = <&pd IMX_SC_R_UART_1>; dmas = <&edma2 15 0 0>, <&edma2 14 0 1>; }; &lpuart2 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 17 0 0>, + <&edma2 16 0 1>; }; &lpuart3 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 19 0 0>, + <&edma2 18 0 1>; }; &i2c0 { diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 3b684e8b2ecc..ed573f4bf6a8 100755 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -28,6 +28,7 @@ serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; + serial4 = &lpuart4; isi0 = &isi_0; isi1 = &isi_1; isi2 = &isi_2; |