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-rw-r--r--arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi49
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-mek.dts11
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi84
3 files changed, 123 insertions, 21 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
index 4c66c3858a15..a8be49e40c87 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
@@ -9,13 +9,10 @@ hsio_subsys: bus@5f000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
+ /* Only supports up to 32bits DMA, map all possible DDR as inbound ranges */
+ dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
ranges = <0x5f000000 0x0 0x5f000000 0x21000000>;
- dma_cap: dma_cap {
- compatible = "dma-capability";
- only-dma-mask32 = <1>;
- };
-
hsio_axi_clk: clock-hsio-axi {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -42,13 +39,27 @@ hsio_subsys: bus@5f000000 {
power-domains = <&pd IMX_SC_R_PCIE_B>;
};
+ phyx1_lpcg: clock-controller@5f090000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f090000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_per_clk>, <&hsio_per_clk>,
+ <&hsio_per_clk>, <&hsio_per_clk>;
+ bit-offset = <0 4 8 16>;
+ clock-output-names = "hsio_phyx1_pclk",
+ "hsio_phyx1_epcs_tx_clk",
+ "hsio_phyx1_epcs_rx_clk",
+ "hsio_phyx1_apb_clk";
+ power-domains = <&pd IMX_SC_R_SATA_0>;
+ };
+
phyx1_crr1_lpcg: clock-controller@5f0b0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f0b0000 0x10000>;
#clock-cells = <1>;
clocks = <&hsio_per_clk>;
- bit-offset = <0>; /* FIXME: not bit 16? */
- clock-output-names = "hsio_phyx1_clk";
+ bit-offset = <16>;
+ clock-output-names = "hsio_phyx1_per_clk";
power-domains = <&pd IMX_SC_R_SERDES_1>;
};
@@ -62,17 +73,22 @@ hsio_subsys: bus@5f000000 {
power-domains = <&pd IMX_SC_R_PCIE_B>;
};
- hsio_gpr: hsio_gpr@0x5f110000 {
- compatible = "fsl,imx8qm-hsio-gpr",
- "fsl,imx6q-iomuxc-gpr", "syscon";
- reg = <0x5f110000 0x70000>; /* csr regs, gpio */
+ misc_crr5_lpcg: clock-controller@5f0f0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f0f0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_per_clk>;
+ bit-offset = <16>;
+ clock-output-names = "hsio_misc_per_clk";
+ power-domains = <&pd IMX_SC_R_HSIO_GPIO>;
};
pcieb: pcie@0x5f010000 {
compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
reg = <0x5f010000 0x10000>, /* Controller reg */
- <0x7ff00000 0x80000>; /* PCI cfg space */
- reg-names = "dbi", "config";
+ <0x7ff00000 0x80000>, /* PCI cfg space */
+ <0x5f110000 0x60000>; /* lpcg, csr, msic, gpio */
+ reg-names = "dbi", "config", "hsio";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -102,10 +118,13 @@ hsio_subsys: bus@5f000000 {
*/
clocks = <&pcieb_lpcg 0>,
<&pcieb_lpcg 1>,
+ <&pcieb_lpcg 2>,
+ <&phyx1_lpcg 0>,
<&phyx1_crr1_lpcg 0>,
<&pcieb_crr3_lpcg 0>,
- <&pcieb_lpcg 2>;
- clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi";
+ <&misc_crr5_lpcg 0>;
+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
+ "pcie_phy", "phy_per","pcie_per", "misc_per";
power-domains = <&pd IMX_SC_R_PCIE_B>,
<&pd IMX_SC_R_SERDES_1>,
<&pd IMX_SC_R_HSIO_GPIO>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 7d16fe65d1a2..f7b41786cb0b 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -392,6 +392,17 @@
status = "okay";
};
+&sata {
+ /* enable the clkreq-gpio if pcie is not enabled */
+ /*
+ * pinctrl-names = "default";
+ * pinctrl-0 = <&pinctrl_pciea>;
+ * clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
+ */
+ ext_osc = <1>;
+ status = "okay";
+};
+
&usbphy1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index 289b4acbfedf..c0d4658c24d7 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
@@ -5,6 +5,10 @@
*/
&hsio_subsys {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
pciea_lpcg: clock-controller@5f050000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f050000 0x10000>;
@@ -17,13 +21,34 @@
power-domains = <&pd IMX_SC_R_PCIE_A>;
};
+ sata_lpcg: clock-controller@5f070000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f070000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_axi_clk>;
+ bit-offset = <16>;
+ clock-output-names = "hsio_sata_clk";
+ power-domains = <&pd IMX_SC_R_SATA_0>;
+ };
+
+ phyx2_lpcg: clock-controller@5f080000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f080000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_per_clk>, <&hsio_per_clk>;
+ bit-offset = <0 4>;
+ clock-output-names = "hsio_phyx2_pclk_0",
+ "hsio_phyx2_pclk_1";
+ power-domains = <&pd IMX_SC_R_PCIE_A>;
+ };
+
phyx2_crr0_lpcg: clock-controller@5f0a0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f0a0000 0x10000>;
#clock-cells = <1>;
clocks = <&hsio_per_clk>;
- bit-offset = <0>; /* FIXME: not bit 16? */
- clock-output-names = "hsio_phyx2_clk";
+ bit-offset = <16>;
+ clock-output-names = "hsio_phyx2_per_clk";
power-domains = <&pd IMX_SC_R_SERDES_0>;
};
@@ -37,11 +62,22 @@
power-domains = <&pd IMX_SC_R_PCIE_A>;
};
+ sata_crr4_lpcg: clock-controller@5f0e0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5f0e0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&hsio_per_clk>;
+ bit-offset = <16>;
+ clock-output-names = "hsio_sata_per_clk";
+ power-domains = <&pd IMX_SC_R_SATA_0>;
+ };
+
pciea: pcie@0x5f000000 {
compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
reg = <0x5f000000 0x10000>, /* Controller reg */
- <0x6ff00000 0x80000>; /* PCI cfg space */
- reg-names = "dbi", "config";
+ <0x6ff00000 0x80000>, /* PCI cfg space */
+ <0x5f110000 0x60000>; /* lpcg, csr, msic, gpio */
+ reg-names = "dbi", "config", "hsio";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -64,10 +100,13 @@
*/
clocks = <&pciea_lpcg 0>,
<&pciea_lpcg 1>,
+ <&pciea_lpcg 2>,
+ <&phyx2_lpcg 0>,
<&phyx2_crr0_lpcg 0>,
<&pciea_crr2_lpcg 0>,
- <&pciea_lpcg 2>;
- clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi";
+ <&misc_crr5_lpcg 0>;
+ clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
+ "pcie_phy", "phy_per","pcie_per", "misc_per";
power-domains = <&pd IMX_SC_R_PCIE_A>,
<&pd IMX_SC_R_SERDES_0>,
<&pd IMX_SC_R_HSIO_GPIO>;
@@ -77,4 +116,37 @@
local-addr = <0x40000000>;
status = "disabled";
};
+
+ sata: sata@5f020000 {
+ compatible = "fsl,imx8qm-ahci";
+ reg = <0x5f020000 0x10000>, /* Controller reg */
+ <0x5f1a0000 0x10000>, /* PHY reg */
+ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */
+ reg-names = "ctl", "phy", "hsio";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sata_lpcg 0>,
+ <&phyx1_lpcg 0>,
+ <&phyx1_lpcg 1>,
+ <&phyx1_lpcg 2>,
+ <&phyx2_crr0_lpcg 0>,
+ <&phyx1_crr1_lpcg 0>,
+ <&pciea_crr2_lpcg 0>,
+ <&pcieb_crr3_lpcg 0>,
+ <&sata_crr4_lpcg 0>,
+ <&misc_crr5_lpcg 0>,
+ <&phyx2_lpcg 0>,
+ <&phyx2_lpcg 1>,
+ <&phyx1_lpcg 3>;
+ clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx",
+ "per_clk0", "per_clk1", "per_clk2",
+ "per_clk3", "per_clk4", "per_clk5",
+ "phy_pclk0", "phy_pclk1", "phy_apbclk";
+ power-domains = <&pd IMX_SC_R_SATA_0>,
+ <&pd IMX_SC_R_PCIE_A>,
+ <&pd IMX_SC_R_PCIE_B>,
+ <&pd IMX_SC_R_SERDES_0>,
+ <&pd IMX_SC_R_SERDES_1>,
+ <&pd IMX_SC_R_HSIO_GPIO>;
+ status = "disabled";
+ };
};
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-01 18:58:42 +0000