diff options
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 532 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 742 |
2 files changed, 632 insertions, 642 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 2f673991710a..2fe9e648a78d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -27,257 +27,47 @@ }; }; - tcm@00800000 { - compatible = "fsl,tcm"; - reg = <0x0 0x00800000 0 0x1000>; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - regulator-name = "can1-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - regulator-name = "can2-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + tcm@00800000 { + compatible = "fsl,tcm"; + reg = <0x0 0x00800000 0 0x1000>; }; }; -&iomuxc { - pinctrl-names = "default"; - - imx8mp-evk { - - pinctrl_flexcan1_reg: flexcan1reggrp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ - >; - }; - - pinctrl_flexcan2_reg: flexcan2reggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f - MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 - MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 - MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 - MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirq { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grp-gpio { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - }; +&A53_0 { + cpu-supply = <&buck2_reg>; }; &fec { @@ -301,31 +91,6 @@ }; }; -&uart1 { /* BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MP_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; - fsl,uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MP_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; - fsl,uart-has-rtscts; - status = "okay"; -}; - &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -440,6 +205,31 @@ }; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + fsl,uart-has-rtscts; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -471,6 +261,206 @@ status = "okay"; }; -&A53_0 { - cpu-supply = <&buck2_reg>; +&iomuxc { + pinctrl-names = "default"; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 62bf403f15a6..6ddd4325fd4a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -123,16 +123,6 @@ }; }; - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - ddr_pmu0: ddr_pmu@3d800000 { compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x0 0x3d800000 0x0 0x400000>; @@ -149,53 +139,47 @@ interrupt-parent = <&gic>; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <8000000>; - arm,no-tick-in-suspend; - interrupt-parent = <&gic>; + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; }; - osc_32k: clock@0 { + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "osc_32k"; }; - osc_24m: clock@1 { + osc_24m: clock-osc-24m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "osc_24m"; }; - clk_ext1: clock@2 { + clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <133000000>; clock-output-names = "clk_ext1"; }; - clk_ext2: clock@3 { + clk_ext2: clock-ext2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <133000000>; clock-output-names = "clk_ext2"; }; - clk_ext3: clock@4 { + clk_ext3: clock-ext3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <133000000>; clock-output-names = "clk_ext3"; }; - clk_ext4: clock@5 { + clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency= <133000000>; @@ -369,6 +353,22 @@ }; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <8000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -382,30 +382,6 @@ #size-cells = <1>; ranges; - clk: clock-controller@30380000 { - compatible = "fsl,imx8mp-ccm"; - reg = <0x30380000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, - <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, - <&clk IMX8MP_AUDIO_PLL1>, - <&clk IMX8MP_AUDIO_PLL2>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <400000000>, <400000000>, <786432000>, - <722534400>; - }; - - src: src@30390000 { - compatible = "fsl,imx8mp-src", "fsl,imx8mq-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; - }; - gpio1: gpio@30200000 { compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; @@ -525,6 +501,30 @@ wakeup-source; }; }; + + clk: clock-controller@30380000 { + compatible = "fsl,imx8mp-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, + <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, <400000000>, <786432000>, + <722534400>; + }; + + src: src@30390000 { + compatible = "fsl,imx8mp-src", "fsl,imx8mq-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; }; aips2: bus@30400000 { @@ -590,7 +590,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x0 0x30820000 0x0 0x10000>; + reg = <0x30820000 0x10000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, <&clk IMX8MP_CLK_ECSPI1_ROOT>; @@ -604,7 +604,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x0 0x30830000 0x0 0x10000>; + reg = <0x30830000 0x10000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, <&clk IMX8MP_CLK_ECSPI2_ROOT>; @@ -618,7 +618,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x0 0x30840000 0x0 0x10000>; + reg = <0x30840000 0x10000>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, <&clk IMX8MP_CLK_ECSPI3_ROOT>; @@ -662,6 +662,36 @@ status = "disabled"; }; + flexcan1: can@308c0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN1_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + stop-mode = <&gpr 0x10 4 0x10 20>; + status = "disabled"; + }; + + flexcan2: can@308d0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308d0000 0x10000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN2_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + stop-mode = <&gpr 0x10 5 0x10 21>; + status = "disabled"; + }; + i2c1: i2c@30a20000 { #address-cells = <1>; #size-cells = <0>; @@ -782,33 +812,30 @@ status = "disabled"; }; - flexcan1: can@308c0000 { - compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; - reg = <0x308c0000 0x10000>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_IPG_ROOT>, - <&clk IMX8MP_CLK_CAN1_ROOT>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8MP_CLK_CAN1>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; - assigned-clock-rates = <40000000>; - stop-mode = <&gpr 0x10 4 0x10 20>; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, + <&clk IMX8MP_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_QSPI>; status = "disabled"; }; - flexcan2: can@308d0000 { - compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; - reg = <0x308d0000 0x10000>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_IPG_ROOT>, - <&clk IMX8MP_CLK_CAN2_ROOT>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8MP_CLK_CAN2>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; - assigned-clock-rates = <40000000>; - stop-mode = <&gpr 0x10 5 0x10 21>; + sdma1: dma-controller@30bd0000 { + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, + <&clk IMX8MP_CLK_SDMA1_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; status = "disabled"; }; @@ -843,36 +870,9 @@ status = "disabled"; }; - flexspi: spi@30bb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,imx8mm-fspi"; - reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, - <&clk IMX8MP_CLK_QSPI_ROOT>; - clock-names = "fspi", "fspi_en"; - assigned-clock-rates = <80000000>; - assigned-clocks = <&clk IMX8MP_CLK_QSPI>; - status = "disabled"; - }; - - sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; - reg = <0x0 0x30bd0000 0x0 0x10000>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, - <&clk IMX8MP_CLK_SDMA1_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - status = "disabled"; - }; - eqos: ethernet@30bf0000 { compatible = "fsl,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; - reg = <0x0 0x30bf0000 0x0 0x10000>; + reg = <0x30bf0000 0x10000>; interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eth_wake_irq", "macirq"; @@ -896,69 +896,6 @@ }; }; - aips4: bus@32c00000 { - compatible = "simple-bus"; - reg = <0x32c00000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - lcdif1: lcd-controller@32e80000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-lcdif1"; - reg = <0x32e80000 0x10000>; - clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, - <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - clock-names = "pix", "disp-axi", "disp-apb"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, - <&clk IMX8MP_CLK_MEDIA_AXI>, - <&clk IMX8MP_CLK_MEDIA_APB>; - assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, - <&clk IMX8MP_SYS_PLL2_1000M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <594000000>, <500000000>, <200000000>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - - lcdif_disp0: port@0 { - reg = <0>; - - lcdif_to_dsim: endpoint { - remote-endpoint = <&dsim_from_lcdif>; - }; - }; - }; - - mipi_dsi: mipi_dsi@32e60000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-mipi-dsim"; - reg = <0x32e60000 0x10000>; - clocks = <&clk IMX8MP_CLK_DUMMY>, - <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; - clock-names = "cfg", "pll-ref"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; - assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; - assigned-clock-rates = <594000000>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - - port@0 { - dsim_from_lcdif: endpoint { - remote-endpoint = <&lcdif_to_dsim>; - }; - }; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&lcdif_disp0>; - }; - - }; - aips5: bus@30c00000 { compatible = "simple-bus"; reg = <0x30c00000 0x400000>; @@ -989,9 +926,9 @@ status = "disabled"; }; - easrc: easrc@30C90000 { + easrc: easrc@30c90000 { compatible = "fsl,imx8mn-easrc"; - reg = <0x30C90000 0x10000>; + reg = <0x30c90000 0x10000>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; clock-names = "mem"; @@ -1046,12 +983,12 @@ }; }; - sdma2: dma-controller@30e10000 { + sdma3: dma-controller@30e00000 { compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; - reg = <0x30e10000 0x10000>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, - <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>; + reg = <0x30e00000 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; @@ -1059,12 +996,12 @@ status = "disabled"; }; - sdma3: dma-controller@30e00000 { + sdma2: dma-controller@30e10000 { compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; - reg = <0x30e00000 0x10000>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, - <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>; + reg = <0x30e10000 0x10000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, + <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; @@ -1091,6 +1028,206 @@ }; }; }; + + aips4: bus@32c00000 { + compatible = "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mipi_dsi: mipi_dsi@32e60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-mipi-dsim"; + reg = <0x32e60000 0x10000>; + clocks = <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + assigned-clock-rates = <594000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + lcdif1: lcd-controller@32e80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif1"; + reg = <0x32e80000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + }; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + isi_0: isi@32e00000{ + compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; + reg = <0x0 0x32e00000 0x0 0x2000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interface = <2 0 2>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + resets = <&isi_resets>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + isi_1: isi@32e02000 { + compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; + reg = <0x0 0x32e02000 0x0 0x2000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + interface = <2 1 2>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + resets = <&isi_resets>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi_0: csi@32e40000 { + compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; + reg = <0x0 0x32e40000 0x0 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>, <125000000>; + bus-width = <4>; + csi-gpr = <&mediamix_gasket0>; + power-domains = <&mipi_phy1_pd>; + resets = <&mipi_csi0_resets>; + status = "disabled"; + }; + + mipi_csi_1: csi@32e50000 { + compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; + reg = <0x0 0x32e50000 0x0 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY2_REF>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY2_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>, <125000000>; + bus-width = <4>; + csi-gpr = <&mediamix_gasket1>; + power-domains = <&mipi_phy2_pd>; + resets = <&mipi_csi1_resets>; + status = "disabled"; + }; + }; + + meidamix-reset { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mediamix_sft_rstn: mediamix-sft-rstn@32ec0000 { + compatible = "fsl,imx8mp-mediamix-sft-rstn"; + reg = <0 0x32ec0000 0 0x4>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "media_apb_root_clk"; + active_low; + power-domains = <&mediamix_pd>; + #reset-cells = <1>; + }; + + mediamix_clk_en: mediamix-clk-en@32ec0004 { + compatible = "fsl,imx8mp-mediamix-clk-en"; + reg = <0 0x32ec0004 0 0x4>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "media_apb_root_clk"; + power-domains = <&mediamix_pd>; + #reset-cells = <1>; + }; + + mediamix_mipi_rst: mediamix-mipi-rst@32ec0008 { + compatible = "fsl,imx8mp-mediamix-mipi-rst"; + reg = <0 0x32ec0008 0 0x4>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "media_apb_root_clk"; + active_low; + power-domains = <&mediamix_pd>; + #reset-cells = <1>; + }; + }; + + mediamix_gasket0: gasket@32ec0060 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x0 0x32ec0060 0x0 0x28>; + }; + + mediamix_gasket1: gasket@32ec0090 { + compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + reg = <0x0 0x32ec0090 0x0 0x28>; }; dma_apbh: dma-apbh@33000000 { @@ -1122,16 +1259,43 @@ status = "disabled"; }; - vpu_vc8000e: vpu_vc8000e@38320000 { - compatible = "nxp,imx8mp-hantro-vc8000e"; - reg = <0x0 0x38320000 0x0 0x10000>; - reg-names = "regs_hantro_vc8000e"; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irq_hantro_vc8000e"; - clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; - clock-names = "clk_hantro_vc8000e", "clk_hantro_vc8000e_bus"; - assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; - assigned-clock-rates = <400000000>, <600000000>; + gpu_3d: gpu3d@38000000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x38000000 0x0 0x8000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "shader", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE_SRC>, + <&clk IMX8MP_CLK_GPU3D_SHADER_SRC>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <1000000000>, + <800000000>, <400000000>; + status = "disabled"; + }; + + gpu_2d: gpu2d@38008000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x38008000 0x0 0x8000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_SRC>, + <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <800000000>, <400000000>; status = "disabled"; }; @@ -1161,43 +1325,16 @@ status = "disabled"; }; - gpu_3d: gpu3d@38000000 { - compatible = "fsl,imx8-gpu"; - reg = <0x0 0x38000000 0x0 0x8000>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, - <&clk IMX8MP_CLK_DUMMY>, - <&clk IMX8MP_CLK_GPU_AXI>, - <&clk IMX8MP_CLK_GPU_AHB>; - clock-names = "core", "shader", "axi", "ahb"; - assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE_SRC>, - <&clk IMX8MP_CLK_GPU3D_SHADER_SRC>, - <&clk IMX8MP_CLK_GPU_AXI>, - <&clk IMX8MP_CLK_GPU_AHB>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, - <&clk IMX8MP_SYS_PLL2_1000M>, - <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <1000000000>, <1000000000>, - <800000000>, <400000000>; - status = "disabled"; - }; - - gpu_2d: gpu2d@38008000 { - compatible = "fsl,imx8-gpu"; - reg = <0x0 0x38008000 0x0 0x8000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, - <&clk IMX8MP_CLK_GPU_AXI>, - <&clk IMX8MP_CLK_GPU_AHB>; - clock-names = "core", "axi", "ahb"; - assigned-clocks = <&clk IMX8MP_CLK_GPU2D_SRC>, - <&clk IMX8MP_CLK_GPU_AXI>, - <&clk IMX8MP_CLK_GPU_AHB>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, - <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <1000000000>, <800000000>, <400000000>; + vpu_vc8000e: vpu_vc8000e@38320000 { + compatible = "nxp,imx8mp-hantro-vc8000e"; + reg = <0x0 0x38320000 0x0 0x10000>; + reg-names = "regs_hantro_vc8000e"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro_vc8000e"; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>; + clock-names = "clk_hantro_vc8000e", "clk_hantro_vc8000e_bus"; + assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>; + assigned-clock-rates = <400000000>, <600000000>; status = "disabled"; }; @@ -1220,12 +1357,9 @@ status = "disabled"; }; - mix_gpu_ml: mix_gpu_ml { - compatible = "fsl,imx8mp-gpu", "fsl,imx8-gpu-ss"; - cores = <&gpu_3d>, <&ml_vipsi>, <&gpu_2d>; - reg = <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x8000000>; - reg-names = "phys_baseaddr", "contiguous_mem"; - status = "disabled"; + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp0>; }; imx_ion: imx_ion { @@ -1233,42 +1367,6 @@ fsl,heap-id = <0>; }; - meidamix-reset { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mediamix_sft_rstn: mediamix-sft-rstn@32ec0000 { - compatible = "fsl,imx8mp-mediamix-sft-rstn"; - reg = <0x0 0x32ec0000 0x0 0x4>; - clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - clock-names = "media_apb_root_clk"; - active_low; - power-domains = <&mediamix_pd>; - #reset-cells = <1>; - }; - - mediamix_clk_en: mediamix-clk-en@32ec0004 { - compatible = "fsl,imx8mp-mediamix-clk-en"; - reg = <0x0 0x32ec0004 0x0 0x4>; - clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - clock-names = "media_apb_root_clk"; - power-domains = <&mediamix_pd>; - #reset-cells = <1>; - }; - - mediamix_mipi_rst: mediamix-mipi-rst@32ec0008 { - compatible = "fsl,imx8mp-mediamix-mipi-rst"; - reg = <0x0 0x32ec0008 0x0 0x4>; - clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - clock-names = "media_apb_root_clk"; - active_low; - power-domains = <&mediamix_pd>; - #reset-cells = <1>; - }; - }; - isi_resets: isi-resets { #address-cells = <1>; #size-cells = <0>; @@ -1333,109 +1431,11 @@ }; }; - mediamix_gasket0: gasket@32ec0060 { - compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; - reg = <0x0 0x32ec0060 0x0 0x28>; - }; - - mediamix_gasket1: gasket@32ec0090 { - compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; - reg = <0x0 0x32ec0090 0x0 0x28>; - }; - - cameradev: camera { - compatible = "fsl,mxc-md", "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + mix_gpu_ml: mix_gpu_ml { + compatible = "fsl,imx8mp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d>, <&ml_vipsi>, <&gpu_2d>; + reg = <0x0 0x40000000 0x0 0x10000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; status = "disabled"; - - isi_0: isi@32e00000{ - compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; - reg = <0x0 0x32e00000 0x0 0x2000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - interface = <2 0 2>; - clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, - <&clk IMX8MP_CLK_MEDIA_APB>, - <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - assigned-clock-rates = <500000000>, <200000000>; - resets = <&isi_resets>; - status = "disabled"; - - cap_device { - compatible = "imx-isi-capture"; - status = "disabled"; - }; - }; - - isi_1: isi@32e02000 { - compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi"; - reg = <0x0 0x32e02000 0x0 0x2000>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - interface = <2 1 2>; - clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, - <&clk IMX8MP_CLK_MEDIA_APB>, - <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - assigned-clock-rates = <500000000>, <200000000>; - resets = <&isi_resets>; - status = "disabled"; - - cap_device { - compatible = "imx-isi-capture"; - status = "disabled"; - }; - }; - - mipi_csi_0: csi@32e40000 { - compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; - reg = <0x0 0x32e40000 0x0 0x10000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <333000000>; - clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, - <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>, - <&clk IMX8MP_CLK_MEDIA_AXI>, - <&clk IMX8MP_CLK_MEDIA_APB>; - clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, - <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, - <&clk IMX8MP_SYS_PLL2_1000M>; - assigned-clock-rates = <333000000>, <125000000>; - bus-width = <4>; - csi-gpr = <&mediamix_gasket0>; - power-domains = <&mipi_phy1_pd>; - resets = <&mipi_csi0_resets>; - status = "disabled"; - }; - - mipi_csi_1: csi@32e50000 { - compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi"; - reg = <0x0 0x32e50000 0x0 0x10000>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <333000000>; - clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, - <&clk IMX8MP_CLK_MEDIA_MIPI_PHY2_REF>, - <&clk IMX8MP_CLK_MEDIA_AXI>, - <&clk IMX8MP_CLK_MEDIA_APB>; - clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, - <&clk IMX8MP_CLK_MEDIA_MIPI_PHY2_REF>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, - <&clk IMX8MP_SYS_PLL2_1000M>; - assigned-clock-rates = <333000000>, <125000000>; - bus-width = <4>; - csi-gpr = <&mediamix_gasket1>; - power-domains = <&mipi_phy2_pd>; - resets = <&mipi_csi1_resets>; - status = "disabled"; - }; }; }; |