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-rw-r--r--arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi8
-rw-r--r--arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi5
-rw-r--r--arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi13
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi41
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi25
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi61
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp.dtsi6
7 files changed, 132 insertions, 27 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 077063e5d124..63590b6ffaf7 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -152,7 +152,6 @@ adma_subsys: bus@59000000 {
};
adma_lpuart0: serial@5a060000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
@@ -166,7 +165,6 @@ adma_subsys: bus@59000000 {
};
adma_lpuart1: serial@5a070000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a070000 0x1000>;
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
@@ -186,7 +184,6 @@ adma_subsys: bus@59000000 {
};
adma_lpuart2: serial@5a080000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a080000 0x1000>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
@@ -206,7 +203,6 @@ adma_subsys: bus@59000000 {
};
adma_lpuart3: serial@5a090000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a090000 0x1000>;
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
@@ -226,7 +222,6 @@ adma_subsys: bus@59000000 {
};
adma_i2c0: i2c@5a800000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a800000 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
@@ -239,7 +234,6 @@ adma_subsys: bus@59000000 {
};
adma_i2c1: i2c@5a810000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a810000 0x4000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
@@ -252,7 +246,6 @@ adma_subsys: bus@59000000 {
};
adma_i2c2: i2c@5a820000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a820000 0x4000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
@@ -265,7 +258,6 @@ adma_subsys: bus@59000000 {
};
adma_i2c3: i2c@5a830000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a830000 0x4000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 68c79baa80bf..59d6afd9d8e5 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -48,7 +48,6 @@ conn_subsys: bus@5b000000 {
};
usdhc1: mmc@5b010000 {
- compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
@@ -65,7 +64,6 @@ conn_subsys: bus@5b000000 {
};
usdhc2: mmc@5b020000 {
- compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>;
@@ -82,7 +80,6 @@ conn_subsys: bus@5b000000 {
};
usdhc3: mmc@5b030000 {
- compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>;
@@ -99,7 +96,6 @@ conn_subsys: bus@5b000000 {
};
fec1: ethernet@5b040000 {
- compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
reg = <0x5b040000 0x10000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
@@ -121,7 +117,6 @@ conn_subsys: bus@5b000000 {
};
fec2: ethernet@5b050000 {
- compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
reg = <0x5b050000 0x10000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index 8d6875cefcf7..73ac3baa76a1 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -12,7 +12,6 @@ lsio_subsys: bus@5d000000 {
<0x08000000 0x0 0x08000000 0x10000000>;
lsio_gpio0: gpio@5d080000 {
- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x5d080000 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -23,7 +22,6 @@ lsio_subsys: bus@5d000000 {
};
lsio_gpio1: gpio@5d090000 {
- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x5d090000 0x10000>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -34,7 +32,6 @@ lsio_subsys: bus@5d000000 {
};
lsio_gpio2: gpio@5d0a0000 {
- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x5d0a0000 0x10000>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -45,7 +42,6 @@ lsio_subsys: bus@5d000000 {
};
lsio_gpio3: gpio@5d0b0000 {
- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x5d0b0000 0x10000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -56,7 +52,6 @@ lsio_subsys: bus@5d000000 {
};
lsio_gpio4: gpio@5d0c0000 {
- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x5d0c0000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -67,7 +62,6 @@ lsio_subsys: bus@5d000000 {
};
lsio_gpio5: gpio@5d0d0000 {
- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x5d0d0000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -78,7 +72,6 @@ lsio_subsys: bus@5d000000 {
};
lsio_gpio6: gpio@5d0e0000 {
- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x5d0e0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -89,7 +82,6 @@ lsio_subsys: bus@5d000000 {
};
lsio_gpio7: gpio@5d0f0000 {
- compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x5d0f0000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -114,7 +106,6 @@ lsio_subsys: bus@5d000000 {
};
lsio_mu0: mailbox@5d1b0000 {
- compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <0>;
@@ -122,14 +113,12 @@ lsio_subsys: bus@5d000000 {
};
lsio_mu1: mailbox@5d1c0000 {
- compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
reg = <0x5d1c0000 0x10000>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
lsio_mu2: mailbox@5d1d0000 {
- compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
reg = <0x5d1d0000 0x10000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
@@ -137,7 +126,6 @@ lsio_subsys: bus@5d000000 {
};
lsio_mu3: mailbox@5d1e0000 {
- compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
reg = <0x5d1e0000 0x10000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
@@ -145,7 +133,6 @@ lsio_subsys: bus@5d000000 {
};
lsio_mu4: mailbox@5d1f0000 {
- compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
reg = <0x5d1f0000 0x10000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
new file mode 100644
index 000000000000..5809324de8df
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&adma_lpcg {
+ compatible = "fsl,imx8qxp-lpcg-adma";
+};
+
+&adma_lpuart0 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&adma_lpuart1 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&adma_lpuart2 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&adma_lpuart3 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&adma_i2c0 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&adma_i2c1 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&adma_i2c2 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&adma_i2c3 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
new file mode 100644
index 000000000000..ea0cd518680b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&conn_lpcg {
+ compatible = "fsl,imx8qxp-lpcg-conn";
+};
+
+&usdhc1 {
+ compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+};
+
+&usdhc2 {
+ compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+};
+
+&fec1 {
+ compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
+};
+
+&fec2 {
+ compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
new file mode 100644
index 000000000000..57979dc4ca77
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&lsio_gpio0 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio1 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio2 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio3 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio4 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio5 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio6 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio7 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_mu0 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu1 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu2 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu3 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu4 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_lpcg {
+ compatible = "fsl,imx8qxp-lpcg-lsio";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 00897f9c84ea..80b19e4e2196 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
@@ -356,6 +356,10 @@
#include "imx8-ss-img.dtsi"
};
+#include "imx8qxp-ss-adma.dtsi"
+#include "imx8qxp-ss-conn.dtsi"
+#include "imx8qxp-ss-lsio.dtsi"
+
&edma2 {
status = "okay";
};
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-01 23:10:17 +0000